Semiconductor integrated circuit

ABSTRACT

There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N 1 , bN 1  of a differential sense amplifier. A latch circuit is connected between nodes N 2 , bN 2 . A data change circuit is connected between the nodes N 1  and bN 2  and between the nodes bN 1  and N 2.  A disconnection circuit is connected between the nodes N 1  and N 2  and between the nodes bN 1  and bN 2 . In a state in which potentials of the input nodes N 1 , bN 1  are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N 1 , bN 1  of the differential sense amplifier.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-228345, filed Jul. 27, 2001, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a circuit which minimizes an offset generated in a semiconductor integrated circuit, that is, a dispersion of threshold voltage of a MOS transistor.

[0004] 2. Description of the Related Art

[0005] In the semiconductor integrated circuit, due to a so-called process dispersion, an operation frequency (history effect) concerning a silicon on insulator (SOI) device, and the like, a dispersion (offset) of a threshold voltage is sometimes generated in a MOS transistor.

[0006] When the offset, that is, the dispersion of the threshold voltage of the MOS transistor is generated, an operation speed is slowed. In some cases, input data cannot accurately be detected, and erroneous data is outputted. Therefore, one of important problems is to remove or minimize the offset.

[0007] A concrete example will be described.

[0008]FIG. 1 shows a differential sense amplifier for use in a semiconductor memory.

[0009] In the semiconductor memory, data of a memory cell is often read out as a micro potential difference generated in a pair of bit lines BL1, bBL1. As is generally known, the micro potential difference is sensed and amplified by the differential sense amplifier.

[0010] Here, among the MOS transistors constituting the differential sense amplifier, when threshold voltages VthP0, VthP1 of P channel MOS transistors QP0, QP1 are different, or when threshold voltages VthN0, VthN1 of N channel MOS transistors QN0, QN1 are different, the offset is generated. This offset reduces a speed for sensing a micro potential difference of the pair of bit lines BL1, bBL1.

[0011] Moreover, when the offset increases, output data is determined only by the offset regardless of the micro potential difference generated in the pair of bit lines BL1, bBL1. As a result, a problem occurs that the input data (readout data of the memory cell) differs from the output data.

[0012] For the SOI device, one of reasons why the offset is generated in the differential sense amplifier is use frequency and history of the MOS transistor.

[0013] This reason will be described hereinafter.

[0014]FIG. 2 shows a device structure of N channel MOS transistors N0, N1 of the differential sense amplifier of FIG. 1.

[0015] Additionally, to simplify the description, it is supposed that the threshold voltages VthP0, VthP1 of the P channel MOS transistors QP0, QP1 of the differential sense amplifier of FIG. 1 are constantly equal to each other, and the threshold voltages VthN0, VthN1 of the N channel MOS transistors N0, N1 are initially equal to each other.

[0016] First, two input nodes N1, bN1 of the differential sense amplifier are precharged, and potentials are both, for example, Vdd. Thereafter, for example, data “1” is read out into the bit line BL1, and data “0” is read out into the bit line bBL1. Moreover, a sense amplifier enable signal SAEN becomes “High (=H)”.

[0017] In this case, the potential of the bit line BL1 remains Vdd, and the potential of the bit line bBL1 drops a little from Vdd. In this case, since both the potentials of the nodes N1, bN1 are higher than the threshold voltages (VthN0=VthN1) of the MOS transistors QN0, QN1, both transistors are turn on.

[0018] However, since a gate potential of the MOS transistor QN1 is a little lower than that of the MOS transistor QN0, a current flowing through the MOS transistor QN1 is a little smaller than a current flowing through the MOS transistor QN0.

[0019] That is to say, a difference of the gate potentials of the MOS transistors QN0, QN1 is a difference of currents flowing through these MOS transistors. As a result, a drop speed of the potential of the node bN1 is higher than that of the node N1.

[0020] Therefore, when the potential of the node bN1 is lower than the threshold voltage of the MOS transistor QN1, the MOS transistor QN1 is turned off, the drop of the potential of the node N1 stops, and the P channel MOS transistor QP1 is turned on.

[0021] Thereafter, the potential of the node N1 turns to a rising direction from a falling direction, and finally returns to Vdd. However, the potential of the node bN1 continues to drop, and finally indicates Vss.

[0022] When the data “1” is read out into the bit line BL1, and the data “0” is read out into the bit line bBL1, only for the N channel MOS transistors QN0, QN1, finally the current flows through the MOS transistor QN0, and the current does not flow through the MOS transistor QN1.

[0023] Here, when the sense amplifier enable signal SAEN changes to “Low (=L)”, the current does not flow through the MOS transistors QN0, QN1, but a charge remains in a substrate (body) A of the MOS transistor QN0. This charge fluctuates the substrate potential of the MOS transistor QN0, and acts in a direction in which the threshold voltage VthN0 is lowered.

[0024] Therefore, when the same data is repeatedly read out into the bit line BL1, for example, when the data “1” is repeatedly read out into the bit line BL1, only the threshold voltage VthN0 of the MOS transistor QN0 drops. Thereby, the readout speed is slowed, or an erroneous sense operation is performed.

[0025] Additionally, a frequency with which the data “1” is read out into the bit line BL1 is substantially the same as a frequency with which the data “0” is read out. In this case, a fluctuation ΔVthN0 of the threshold voltage VthN0 of the MOS transistor QN0 becomes substantially the same as a fluctuation ΔVthN1 of the threshold voltage VthN1 of the MOS transistor QN1, and there is no problem.

[0026] Moreover, the charge accumulated in a substrate A naturally disappears with an elapse of sufficient time after the differential sense amplifier is bought into an inoperative state (SAEN=“L”). However, when the operation of the differential sense amplifier is repeatedly performed, the next readout operation is started before the charge accumulated in the substrate A becomes equal to the charge accumulated in a substrate B. Therefore, as described above, the readout speed is slowed, or the erroneous sense operation is performed.

[0027] Additionally, as a technique of reducing the offset by the fluctuation of the substrate potential, a technique of connecting the substrate to a source of the MOS transistor, a technique of fixing the substrate at a constant potential, and the like have heretofore been known.

[0028] However, in any one of the techniques, it is necessary to dispose a contact portion with respect to the substrate, and therefore a problem of a drop of circuit capability due to an increase of gate capacity occurs. Moreover, any one of the techniques is effective for minimizing the fluctuation of the substrate potential of the SOI device, but it is impossible to minimize the fluctuation of the threshold voltage caused by the process dispersion.

[0029] Therefore, there has been a demand for a technique of minimizing the offset (dispersion of the threshold voltage of the MOS transistor) resulting from the process dispersion or the operation frequency of the SOI device by a circuit operational method, and preventing the drop of the operation speed or the erroneous sense operation caused by the offset.

BRIEF SUMMARY OF THE INVENTION

[0030] According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: an inner circuit; a first circuit which supplies a first signal for obtaining output data dependent on a state of the inner circuit to the inner circuit; a latch circuit which latches the output data; and a second circuit which supplies a second signal for returning the state of the inner circuit to a normal state based on the output data to the inner circuit.

[0031] According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first circuit which supplies a first signal for obtaining output data dependent on a mismatch of a threshold voltage of a MOS transistor to the MOS transistor; a latch circuit which latches the output data; and a second circuit which supplies a second signal for eliminating the mismatch of the threshold voltage of the MOS transistor based on the output data to the MOS transistor.

[0032] According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of the first and second nodes; a latch circuit connected between third and fourth nodes; a data change circuit which controls electric connection or disconnection of the first and fourth nodes and electric connection or disconnection of the second and third nodes; and a disconnection circuit which controls electric disconnection or connection of the first and third nodes and electric disconnection or connection of the second and fourth nodes.

[0033] According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of the first and second nodes; a latch circuit connected between the first and second nodes; a disconnection circuit which controls electric disconnection or connection of the first node and a third node and electric disconnection or connection of the second node and a fourth node; and a data change circuit which controls electric connection or disconnection of the first and fourth nodes and electric connection or disconnection of the second and third nodes.

[0034] According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of the first and second nodes; a latch circuit connected between the first and second nodes; and a data change circuit which controls electric connection or disconnection of the first node and a first inner node of the latch circuit and electric connection or disconnection of the second node and a second inner node of the latch circuit.

[0035] According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of the first and second nodes; a latch circuit connected between third and fourth nodes; a data change circuit which controls electric connection or disconnection of the first node and a first inner node of the latch circuit and electric connection or disconnection of the second node and a second inner node of the latch circuit; and a disconnection circuit which controls electric disconnection or connection of the first and third nodes and electric disconnection or connection of the second and fourth nodes.

[0036] According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a memory cell array; a plurality of sense amplifier arrays corresponding to the memory cell array; an auxiliary array including a first cell connected between a first bit line and a first power terminal and a second cell connected between a second bit line and a second power terminal; a disconnection circuit which is connected between the first bit line and first node and between the second bit line and second node and which controls electric disconnection or connection of the first bit line and first node and electric disconnection or connection of the second bit line and second node; a sense amplifier connected between the first and second nodes; an equalize circuit which equalizes potentials of the first and second nodes; a latch circuit connected between the first and second nodes; a data change circuit which controls electric connection or disconnection of the first node and a first inner node of the latch circuit and electric connection or disconnection of the second node and a second inner node of the latch circuit; and a refresh control circuit to monitor data of the first inner node or the second inner node and to stop operations of the sense amplifier and sense amplifier array, when the data changes.

[0037] According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a memory cell array; a plurality of sense amplifier arrays corresponding to the memory cell array; a first auxiliary array including a first cell connected between a first bit line and first power terminal and a second cell connected between a second bit line and second power terminal; a first disconnection circuit which is connected between the first bit line and a first node and between the second bit line and a second node and which controls electric disconnection or connection of the first bit line and first node and electric disconnection or connection of the second bit line and second node; a first sense amplifier connected between the first and second nodes; a first equalize circuit which equalizes potentials of the first and second nodes; a first latch circuit connected between the first and second nodes; a first data change circuit which controls electric connection or disconnection of the first node and a first inner node of the latch circuit and electric connection or disconnection of the second node and a second inner node of the latch circuit; a second auxiliary array including a third cell connected between a third bit line and the second power terminal and a fourth cell connected between a fourth bit line and the first power terminal; a second disconnection circuit which is connected between the third bit line and a third node and between the fourth bit line and a fourth node and which controls electric disconnection or connection of the third bit line and third node and electric disconnection or connection of the fourth bit line and fourth node; a second sense amplifier connected between the third and fourth nodes; a second equalize circuit which equalizes potentials of the third and fourth nodes; a second latch circuit connected between the third and fourth nodes; a second data change circuit which controls electric connection or disconnection of the third node and a third inner node of the latch circuit and electric connection or disconnection of the fourth node and a fourth inner node of the latch circuit; and a refresh control circuit to monitor data of the first or second inner node and data of the third or fourth inner node and to stop operations of the first and second sense amplifiers and sense amplifier array, when these data both change.

[0038] According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: an array including a plurality of program elements; a decoder to select a first row of the array including a first program element to output first data, when input data having a specific value is inputted; a refresh control circuit which allows the decoder to select a second row of the array including a second program element to output second data different from the first data periodically or at random; and a sense amplifier which amplifies the first and second data.

[0039] According to a tenth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a logic circuit to output specific data, when first input data having a specific value is inputted; and a refresh control circuit which inputs second input data having the specific value into the logic circuit instead of the first input data periodically or at random, wherein a probability with which the first input data indicates the specific value is lower than a probability with which the first input data indicates a value other than the specific value.

[0040] According to an eleventh aspect of the present invention, there is provided a method of minimizing an offset of a differential sense amplifier, comprising: a first step of operating the differential sense amplifier in a state in which two input potentials of the differential sense amplifier are equalized, and obtaining output data of the differential sense amplifier; a second step of allowing a latch circuit to latch the output data of the differential sense amplifier; and a third step of inputting data having a value reverse to a value of the output data of the differential sense amplifier into the differential sense amplifier.

[0041] According to a twelfth aspect of the present invention, there is provided a method of minimizing an offset of a differential sense amplifier, comprising: a first step of counting the number of inputs of first data into the differential sense amplifier and the number of inputs of second data reverse to the first data into the differential sense amplifier; and a second step of executing an operation of minimizing a dispersion of a threshold voltage of a MOS transistor constituting the differential sense amplifier, when a difference between the number of inputs of the first data and the number of inputs of the second data indicates a constant or more value.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0042]FIG. 1 is a diagram showing an example of a differential sense amplifier;

[0043]FIG. 2 is a diagram showing a state of a MOS transistor in the differential sense amplifier;

[0044]FIG. 3 is a diagram showing an outline of a semiconductor integrated circuit according to a first embodiment of the present invention;

[0045]FIG. 4 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 3;

[0046]FIG. 5 is a diagram showing an example of the differential sense amplifier;

[0047]FIG. 6 is a diagram showing one example of a refresh control circuit;

[0048]FIG. 7 is a diagram showing that the semiconductor integrated circuit of FIG. 4 is applied to a semiconductor memory;

[0049]FIG. 8 is a diagram showing an operation of the semiconductor integrated circuit of FIG. 7;

[0050]FIG. 9 is a diagram showing the operation of the semiconductor integrated circuit of FIG. 7;

[0051]FIG. 10 is a diagram showing a modification example of the semiconductor integrated circuit of FIG. 7;

[0052]FIG. 11 is a diagram showing a modification example of the semiconductor integrated circuit of FIG. 7;

[0053]FIG. 12 is a diagram showing an outline of the semiconductor integrated circuit according to a second embodiment of the present invention;

[0054]FIG. 13 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 12;

[0055]FIG. 14 is a diagram showing an outline of the semiconductor integrated circuit according to a third embodiment of the present invention;

[0056]FIG. 15 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 14;

[0057]FIG. 16 is a diagram showing an operation of the semiconductor integrated circuit of FIG. 15;

[0058]FIG. 17 is a diagram showing the operation of the semiconductor integrated circuit of FIG. 15;

[0059]FIG. 18 is a diagram showing a constitution of a general SRAM;

[0060]FIG. 19 is a diagram showing the outline of the semiconductor integrated circuit according to a fourth embodiment of the present invention;

[0061]FIG. 20 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 19;

[0062]FIG. 21 is a diagram showing a state of the MOS transistor in the differential sense amplifier;

[0063]FIG. 22 is a diagram showing the state of the MOS transistor in the differential sense amplifier;

[0064]FIG. 23 is a diagram showing the state of the MOS transistor in the differential sense amplifier;

[0065]FIG. 24 is a diagram showing the outline of the semiconductor integrated circuit according to a fifth embodiment of the present invention;

[0066]FIG. 25 is a diagram showing the outline of the semiconductor integrated circuit according to a sixth embodiment of the present invention;

[0067]FIG. 26 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 25;

[0068]FIG. 27 is a diagram showing a modification example of the semiconductor integrated circuit of FIG. 26;

[0069]FIG. 28 is a diagram showing an example of the differential sense amplifier;

[0070]FIG. 29 is a diagram showing the operation of the semiconductor integrated circuit of FIG. 26;

[0071]FIG. 30 is a diagram showing the operation of the semiconductor integrated circuit of FIG. 26;

[0072]FIG. 31 is a diagram showing the outline of the semiconductor integrated circuit according to a seventh embodiment of the present invention;

[0073]FIG. 32 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 31;

[0074]FIG. 33 is a diagram showing the outline of the semiconductor integrated circuit according to an eighth embodiment of the present invention;

[0075]FIG. 34 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 33;

[0076]FIG. 35 is a diagram showing the outline of the semiconductor integrated circuit according to the eighth embodiment of the present invention;

[0077]FIG. 36 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 35;

[0078]FIG. 37 is a diagram showing a concrete example of the semiconductor integrated circuit of FIG. 35;

[0079]FIG. 38 is a diagram showing the outline of the semiconductor integrated circuit according to a ninth embodiment of the present invention;

[0080]FIG. 39 is a diagram showing a part of a logic array of FIG. 38;

[0081]FIG. 40 is a diagram showing the outline of the semiconductor integrated circuit according to a tenth embodiment of the present invention;

[0082]FIG. 41 is a diagram showing a method 1 of minimizing an offset according to the present invention;

[0083]FIG. 42 is a diagram showing a method 2 of minimizing the offset according to the present invention; and

[0084]FIG. 43 is a diagram showing a method 3 of minimizing the offset according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0085] A semiconductor integrated circuit according to one example of the present invention will be described hereinafter in detail with reference to the drawings.

[0086] [First Embodiment]

[0087] 1. Outline

[0088]FIG. 3 shows a semiconductor integrated circuit according to a first embodiment of the present invention.

[0089] A differential sense amplifier 11 is connected between nodes N1, bN1. The differential sense amplifier includes a constitution, for example, shown in FIG. 1. Moreover, an equalize circuit 12 for equalizing potentials of the nodes N1, bN1 is connected between the nodes N1, bN1.

[0090] On the other hand, a latch circuit 13 is connected between nodes N2, bN2. A data change circuit 14 is connected between the nodes N1 and bN2, and also connected between the nodes bN1 and N2. The data change circuit 14 has a function of electrically connecting or disconnecting the nodes N1 and bN2 and electrically connecting or disconnecting the nodes bN1 and N2.

[0091] A disconnection circuit 15 is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. The disconnection circuit 15 has a function of electrically disconnecting or connecting the nodes N1 and N2 and electrically disconnecting or connecting the nodes bN1 and bN2.

[0092] An operation principle of the semiconductor integrated circuit of FIG. 3 will briefly be described.

[0093] It is assumed that the differential sense amplifier 11 has an offset.

[0094] First, the equalize circuit 12 equalizes potentials of the nodes N1, bN2. Thereafter, the differential sense amplifier 11 is operated. At this time, since the potential difference is not generated in two input nodes N1, bN2 of the differential sense amplifier 11, the output data is determined depending only on the offset of the differential sense amplifier 11.

[0095] The output data (offset information) is latched by the latch circuit 13. At this time, the data change circuit 14 electrically connects the nodes N1 and bN2 and electrically connects the nodes bN1 and N2. Moreover, the disconnection circuit 15 electrically disconnects the nodes N1 and N2 and electrically disconnects the nodes bN1 and bN2.

[0096] Therefore, the output data of the node N1 is transferred to the node bN2, and the output data of the node bN1 is transferred to the node N2. That is, the data having a value reverse to the value of the output data of the differential sense amplifier 11 is latched by the latch circuit 13.

[0097] Thereafter, the data change circuit 14 electrically disconnects the nodes N1 and bN2 and electrically disconnects the nodes bN1 and N2. Moreover, the disconnection circuit 15 electrically connects the nodes N1 and N2 and electrically connects the nodes bN1 and bN2.

[0098] Therefore, the output data of the node N2 is transferred to the node N1, and the output data of the node bN2 is transferred to the node bN1. That is, the data having a value reverse to the value of the output data of the differential sense amplifier 11, that is, data for reducing the offset is inputted into the differential sense amplifier 11.

[0099] In this manner, according to the present invention, the data acting in a direction in which the offset of the differential sense amplifier 11 is reduced is inputted into the differential sense amplifier 11, and the offset of the differential sense amplifier 11 is minimized.

[0100] 2. Concrete Example

[0101]FIG. 4 shows a concrete example of the semiconductor integrated circuit of FIG. 3.

[0102] The differential sense amplifier 11 is constituted of P channel MOS transistors QP0, QP1 and N channel MOS transistors QN0, QN1, QN2.

[0103] Gates of the MOS transistors QP0, QN0 are connected to the node N1 and drains of the MOS transistors QP1, QN1. The gates of the MOS transistors QP1, QN1 are connected to the node bN1 and the drains of the MOS transistors QP0, QN0.

[0104] Sources of the MOS transistors QP0, QP1 are connected to an inner power node Vdd, and the MOS transistor QN2 is connected between the sources of the MOS transistors QN0, QN1 and a ground point. A sense amplifier enable signal SAEN is inputted into the gate of the MOS transistor QN2.

[0105] The equalize circuit 12 is constituted of N channel MOS transistors QN3, QN4, QN5. The MOS transistor QN3 is connected between the nodes N1 and bN1, the MOS transistor QN4 is connected between the inner power node Vdd and node N1, and the MOS transistor QN5 is connected between the inner power node Vdd and node bN1.

[0106] An equalize signal EQ is inputted into the gates of the MOS transistors QN3, QN4, QN5. When the equalize signal EQ reaches “H”, both the nodes N1, bN1 are set to an inner power potential Vdd.

[0107] Additionally, in the present example, the equalize circuit 12 sets both the nodes N1, bN1 to the inner power potential Vdd. Instead of this, for example, the equalize circuit 12 may be modified so as to set the nodes N1, bN1 to Vdd/2. In this case, the differential sense amplifier 11 is also modified, for example, as shown in FIG. 5.

[0108] The latch circuit 13 is constituted of two flip-flop connected inverters 11, 12 connected between nodes N3, bN3, an N channel MOS transistor (transfer gate) QN6 connected between nodes N2 and N3, and an N channel MOS transistor (transfer gate) QN7 connected between nodes bN2 and bN3.

[0109] When a control signal DWL indicates “H”, the nodes N2 and N3 are short-circuited, and the nodes bN2 and bN3 are short-circuited.

[0110] Additionally, the latch circuit 13 can be constituted, for example, in the same manner as the memory cell. When the memory cell is a static memory cell, as in the present example, the latch circuit 13 can have the same constitution (dummy cell) as the static memory cell. In this case, the control signal DWL is supplied to the gates of the MOS transistors QN6, QN7 from a dummy word line.

[0111] The data change circuit 14 is constituted of MOS transistors QP4, QN8 connected between the nodes N1 and bN2, and MOS transistors QP5, QN9 connected between the nodes bN1 and N2. When an offset check signal OC indicates “H”, the MOS transistors QP4, QP5, QN8, QN9 are turned on, and the nodes N1 and bN2, and the nodes N1 and bN2 are electrically connected.

[0112] The disconnection circuit 15 is constituted of a P channel MOS transistor QP6 connected between the nodes N1, N2, and a P channel MOS transistor QP7 connected between the nodes bN1, bN2. When the sense amplifier enable signal SAEN indicates “H”, the nodes N1 and N2, and the nodes bN1 and bN2 are electrically disconnected.

[0113]FIG. 6 shows a main part of a refresh control circuit which outputs the sense amplifier enable signal SAEN.

[0114] A refresh control circuit 16 includes a refresh signal generation circuit 17 and OR circuit OR1. The refresh signal generation circuit 17 outputs a refresh signal REFRESH which indicates “H” in a mode to minimize the offset of the differential sense amplifier.

[0115] In a normal readout mode, when the sense amplifier enable signal SAEN inputted into the OR circuit OR1 reaches “H”, an output signal SEAN of the OR circuit OR1 also reaches “H”.

[0116] Moreover, in a mode other than the normal readout mode, the sense amplifier enable signal SAEN inputted into the OR circuit OR1 indicates “L”.

[0117] At this time, when the mode to minimize the offset of the differential sense amplifier is executed, the refresh signal REFRESH reaches “H”, and therefore the output signal SEAN of the OR circuit OR1 also reaches “H”. On the other hand, when the mode to minimize the offset of the differential sense amplifier is not executed, the refresh signal REFRESH indicates “L”, and therefore the output signal SEAN of the OR circuit OR1 also indicates “L”.

[0118] 3. Application Example 1

[0119]FIG. 7 shows a first example in which the semiconductor integrated circuit of FIG. 4 is applied to a semiconductor memory.

[0120] A memory cell array 18 is constituted of an array of static memory cells or dynamic memory cells. A bit line BL1 is connected to the node N2 via an N channel MOS transistor QN10 as a clamp circuit 19. Moreover, a bit line bBL1 is connected to the node bN2 via an N channel MOS transistor QN11 as the clamp circuit 19.

[0121] 4. Operation

[0122] An operation of the semiconductor integrated circuit of FIG. 7 will be described.

[0123] In the normal readout mode, the data of the memory cell is read out as the potential difference of the pair of bit lines BL1, bBL1, and the potential difference is sensed and amplified by the differential sense amplifier 11.

[0124] Here, with the SOI device, unless the number of readouts of “1” data is equal to the number of readouts of “0” data with respect to the same differential sense amplifier 11 (e.g., when only the same data is continuously read out), the substrate potential of the MOS transistor having a large number of operations fluctuates, and the offset (dispersion of the threshold value of the MOS transistor) is generated in the differential sense amplifier 11.

[0125] To minimize the offset, according to the present invention, in the mode other than the normal readout mode, the following operation is continuously or intermittently performed until the offset is eliminated or sufficiently reduced.

[0126] (1) Offset Check Cycle (see FIG. 8)

[0127] The offset of the differential sense amplifier 11 is checked in this cycle.

[0128] First, it is checked whether the differential sense amplifier 11 is used in a normal operation mode. It is confirmed that the differential sense amplifier 11 is not used, and the refresh signal REFRESH is then set to “H”.

[0129] After the equalize signal EQ is set to “H”, and the nodes N1, bN1 are set to the inner power potential Vdd, the equalize signal EQ is set to “L”.

[0130] Thereafter, the sense amplifier enable signal SAEN is set to “H”, and simultaneously or a little later the offset check signal OC is set to “H”.

[0131] When the offset check signal OC reaches “H”, the nodes N1 and bN2 are electrically connected, and the nodes bN1 and N2 are electrically connected. Moreover, when the sense amplifier enable signal SAEN reaches “H”, the nodes N1 and N2 are electrically disconnected, and the nodes bN1 and bN2 are electrically disconnected.

[0132] Furthermore, since the sense amplifier enable signal SAEN reaches “H”, the differential sense amplifier 11 is brought into an operative state. Since the potential difference is not generated in the nodes N1, bN1 of the differential sense amplifier 11, the output data of the differential sense amplifier 11 is determined only by the offset of the differential sense amplifier 11.

[0133] That is, in response to the offset of the differential sense amplifier 11, one of the nodes N1, bN1 turns into “1” state (=Vdd), and the other turns into “0” state (=Vss). Additionally, the data outputted to the node N1 is transferred to the node bN2, and the data outputted to the node bN1 is transferred to N2.

[0134] Moreover, when the control signal DWL reaches “H”, the MOS transistors QN6, QN7 are turned on, and therefore the data of the nodes N2, bN2 is latched by the latch circuit 13.

[0135] For example, it is supposed that “1” is read out into the node N1 and “0” is read out into the node bN1 with a high frequency in the normal readout mode.

[0136] In this case, the threshold voltage of the MOS transistor QN0 in the differential sense amplifier 11 is lower than usual, and the threshold voltage of the MOS transistor QP1 in the differential sense amplifier 11 is higher than usual. Therefore, when the inner power potential Vdd is given to the nodes N1, bN1 in an offset check cycle, the potential of the node bN1 drops, “1” is outputted to the node N1, and “0” is outputted to the node bN1.

[0137] Moreover, the “1” data of the node N1 is transferred to the node bN2 via the data change circuit 14, and the “0” data of the node bN1 is transferred to the node N2 via the data change circuit 14. Therefore, the node N3 of the latch circuit 13 turns into the “0” state, and the node bN3 turns into the “1” state.

[0138] (2) Refresh Cycle (see FIG. 9)

[0139] The offset of the differential sense amplifier 11 is minimized in this cycle.

[0140] First, it is checked whether the differential sense amplifier 11 is used in the normal operation mode, it is confirmed that the differential sense amplifier 11 is not used, and the refresh signal REFRESH is then set to “H”.

[0141] After the equalize signal EQ is set to “H”, and the nodes N1, bN1 are set to the inner power potential Vdd, the equalize signal EQ is set to “L”.

[0142] Thereafter, when the control signal DWL is set to “H”, the data latched by the latch circuit 13 is outputted to the nodes N2, bN2.

[0143] For example, when the node N3 of the latch circuit 13 is in the “0” state, and the node bN3 is in the “1” state, the “0” data is outputted to the node N2, and the “1” data is outputted to the node bN2. Moreover, at this time, since the sense amplifier enable signal SAEN indicates “L”, the P channel MOS transistors QP6, QP7 are in the on state. Therefore, the “0” data of the node N2 is transferred to the node N1, and the “1” data of the node bN2 is transferred to the node bN1.

[0144] Thereafter, the sense amplifier enable signal SAEN is set to “H”. When the sense amplifier enable signal SAEN reaches “H”, the differential sense amplifier 11 is brought into the operative state. Since the data of the latch circuit 13 is outputted to the nodes N1, bN1 of the differential sense amplifier 11, the output data of the differential sense amplifier 11 is determined by the data of the latch circuit 13.

[0145] Here, the data latched by the latch circuit 13 is reverse to the data outputted from the differential sense amplifier 11 in the offset check cycle. In other words, in the refresh cycle, the data reverse to the data inputted into the differential sense amplifier 11 with a high frequency in the normal readout mode is inputted into the differential sense amplifier 11.

[0146] Therefore, in the refresh cycle, the MOS transistor different from the MOS transistor turned on by the data inputted in the normal readout mode with the high frequency is turned on, and the threshold voltage of the MOS transistor fluctuates in a direction in which the offset of the differential sense amplifier 11 is reduced.

[0147] For example, in the normal readout mode, when the “1” data is read out into the node N1 and the “0” data is read out into the node bN1 with the high frequency, the node N3 of the latch circuit 13 turns into the “0” state and the node bN3 turns into the “1” state in the offset check cycle. Therefore, in the refresh cycle, the “0” data is inputted into the node N1 of the differential sense amplifier 11, and the “1” data is inputted into the node bN1.

[0148] In this case, since the MOS transistors QP0, QN1 in the differential sense amplifier 11 are brought into the on state, the threshold voltage of the N channel MOS transistor QN1 drops, and the threshold voltage of the P channel MOS transistor QP1 rises. That is, the threshold voltage of the MOS transistor QN1 fluctuates in a direction in which the threshold voltage becomes equal to the threshold voltage of the MOS transistor QN0 in a state lower than usual. The threshold voltage of the MOS transistor QP0 fluctuates in a direction in which the threshold voltage becomes equal to the threshold voltage of the MOS transistor QP1 in a state higher than usual.

[0149] In this manner, since the data reverse to the data inputted into the differential sense amplifier 11 in the normal readout mode with the high frequency is inputted into the differential sense amplifier 11 in the refresh cycle, the offset of the differential sense amplifier 11 is minimized.

[0150] Additionally, in the above-described operation (offset check cycle and refresh cycle), a control signal CLAMP is set to “L”, MOS transistors QN10, QN11 are turned off, and the nodes N2, bN2 may electrically be disconnected from the pair of bit lines BL1, bBL1. In this case, in an input/output operation with respect to the latch circuit 13, it is unnecessary to charge a large capacity (bit line pair), and a high-speed operation can be realized.

[0151] 5. Application Example 2

[0152]FIG. 10 shows a second example in which the semiconductor integrated circuit of FIG. 4 is applied to the semiconductor memory.

[0153] The memory cell array 18 is constituted of the array of static memory cells or dynamic memory cells.

[0154] As characteristics of a memory circuit of the present example, a plurality of bit lines (four bit lines in the present example) BL1, BL2, BL3, BL4 are connected to the node N2 via a column selection circuit 20. Similarly, a plurality of bit lines bBL1, bBL2, bBL3, bBL4 are connected to the node bN2 via the column selection circuit 20.

[0155] When the present invention is applied to the semiconductor memory including a plurality of differential sense amplifiers, a circuit to minimize the offset (or an operation method) is applied to each differential sense amplifier 11. Therefore, the present invention can be applied to the semiconductor memory irrespective of the number of bit line pairs connected to the differential sense amplifier 11.

[0156] 6. Application Example 3

[0157]FIG. 11 shows a third example in which the semiconductor integrated circuit of FIG. 4 is applied to the semiconductor memory.

[0158] The present example relates to a static random access memory (SRAM).

[0159] A memory cell 13A of the SRAM is constituted of two flip-flop connected inverters and two transfer gates. For example, the constitution of the memory cell 13A is the same as that of the latch circuit 13 of FIG. 7.

[0160] Therefore, in the present example, the memory cell 13A in the memory cell array 18 is used as the latch circuit which latches the offset information.

[0161] When the offset information is latched in the memory cell 13A in the memory cell array 18 in this manner, it is unnecessary to newly dispose the latch circuit in a conventional semiconductor memory, and an increase of chip size can be suppressed.

[0162] 7. Conclusion

[0163] According to the semiconductor integrated circuit according to the first embodiment of the present invention, the offset resulting from the process dispersion or the operation frequency of the SOI device (dispersion of the threshold voltage of the MOS transistor) is minimized by a circuit operational technique, and the drop of the operation speed and the erroneous sense operation can be prevented from being caused by the offset.

[0164] [Second Embodiment]

[0165] 1. Outline

[0166]FIG. 12 shows the semiconductor integrated circuit according to a second embodiment of the present invention.

[0167] As compared with the semiconductor integrated circuit of FIG. 3, the semiconductor integrated circuit of the present example is characterized in that the positions (or layout) of the latch circuit 13, data change circuit 14, and disconnection circuit 15 are different.

[0168] For example, a case in which the present invention is applied to the semiconductor memory is considered. Then, in the example of FIG. 3, the latch circuit 13, data change circuit 14, and disconnection circuit 15 are disposed between the differential sense amplifier 11 and memory cell array. On the other hand, in the present example, the latch circuit 13, data change circuit 14, and disconnection circuit 15 are disposed between the differential sense amplifier 11 and data input/output circuit.

[0169] In the present example, the latch circuit 13 is disposed on a data input/output circuit side of the differential sense amplifier 11. For example, with the SRAM, the latch circuit for temporarily holding the data is usually disposed on the data input/output circuit side of the differential sense amplifier 11. Therefore, the offset information of the differential sense amplifier 11 can also be latched in the latch circuit.

[0170] A connection relation of the semiconductor integrated circuit of the present invention will be described hereinafter.

[0171] The differential sense amplifier 11 is connected between the nodes N1, bN1. The differential sense amplifier includes the constitution, for example, shown in FIG. 1. Moreover, the equalize circuit 12 for equalizing the potentials of the nodes N1, bN1 is connected between the nodes N1, bN1.

[0172] On the other hand, the latch circuit 13 is connected between the nodes N2, bN2. The data change circuit 14 is connected between the nodes N1 and bN2, and also connected between the nodes bN1 and N2. The data change circuit 14 has a function of electrically connecting or disconnecting the nodes N1 and bN2 and electrically connecting or disconnecting the nodes bN1 and N2.

[0173] The disconnection circuit 15 is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. The disconnection circuit 15 has a function of electrically disconnecting or connecting the nodes N1 and N2 and electrically disconnecting or connecting the nodes bN1 and bN2.

[0174] The operation principle of the semiconductor integrated circuit of FIG. 12 will briefly be described.

[0175] It is assumed that the differential sense amplifier 11 has the offset.

[0176] First, the equalize circuit 12 equalizes the potentials of the nodes N1, N2. Thereafter, the differential sense amplifier 11 is operated. At this time, since the potential difference is not generated in two input nodes N1, N2 of the differential sense amplifier 11, the output data is determined depending only on the offset of the differential sense amplifier 11.

[0177] The output data (offset information) is latched by the latch circuit 13. At this time, the data change circuit 14 electrically connects the nodes N1 and bN2 and electrically connects the nodes bN1 and N2. Moreover, the disconnection circuit 15 electrically disconnects the nodes N1 and N2 and electrically disconnects the nodes bN1 and bN2.

[0178] Therefore, the output data of the node N1 is transferred to the node bN2, and the output data of the node bN1 is transferred to the node N2. That is, the data having the value reverse to the value of the output data of the differential sense amplifier 11 is latched by the latch circuit 13.

[0179] Thereafter, the data change circuit 14 electrically disconnects the nodes N1 and bN2 and electrically disconnects the nodes bN1 and N2. Moreover, the disconnection circuit 15 electrically connects the nodes N1 and N2 and electrically connects the nodes bN1 and bN2.

[0180] Therefore, the output data of the node N2 is transferred to the node N1, and the output data of the node bN2 is transferred to the node bN1. That is, the data having the value reverse to the value of the output data of the differential sense amplifier 11, that is, the data for reducing the offset is inputted into the differential sense amplifier 11.

[0181] In this manner, according to the present invention, the data acting in the direction in which the offset of the differential sense amplifier 11 is reduced is inputted into the differential sense amplifier 11, and the offset of the differential sense amplifier 11 is minimized.

[0182] 2. Concrete Example

[0183]FIG. 13 shows a concrete example of the semiconductor integrated circuit of FIG. 12.

[0184] The differential sense amplifier 11 is constituted of P channel MOS transistors QP0, QP1 and N channel MOS transistors QN0, QN1, QN2.

[0185] The gates of the MOS transistors QP0, QN0 are connected to the node N1 and the drains of the MOS transistors QP1, QN1. The gates of the MOS transistors QP1, QN1 are connected to the node bN1 and the drains of the MOS transistors QP0, QN0.

[0186] The sources of the MOS transistors QP0, QP1 are connected to the inner power node Vdd, and the MOS transistor QN2 is connected between the sources of the MOS transistors QN0, QN1 and the ground point. The sense amplifier enable signal SAEN is inputted into the gate of the MOS transistor QN2.

[0187] The equalize circuit 12 is constituted of N channel MOS transistors QN3, QN4, QN5. The MOS transistor QN3 is connected between the nodes N1 and bN1, the MOS transistor QN4 is connected between the inner power node Vdd and node N1, and the MOS transistor QN5 is connected between the inner power node Vdd and node bN1.

[0188] The equalize signal EQ is inputted into the gates of the MOS transistors QN3, QN4, QN5. When the equalize signal EQ reaches “H”, both the nodes N1 and bN1 are set to the inner power potential Vdd.

[0189] Additionally, in the present example, the equalize circuit 12 sets both the nodes N1, bN1 to the inner power potential Vdd. However, instead of this, for example, the equalize circuit 12 may be modified so as to set the nodes N1, bN1 to Vdd/2. In this case, the differential sense amplifier 11 is also modified, for example, as shown in FIG. 5.

[0190] The latch circuit 13 is constituted of two flip-flop connected inverters 11, 12 connected between the nodes N3, bN3, the N channel MOS transistor (transfer gate) QN6 connected between nodes N2 and N3, and the N channel MOS transistor (transfer gate) QN7 connected between nodes bN2 and bN3.

[0191] When the control signal DWL indicates “H”, the nodes N2 and N3 are short-circuited, and the nodes bN2 and bN3 are short-circuited.

[0192] Additionally, the latch circuit 13 can be constituted, for example, in the same manner as the memory cell. When the memory cell is the static memory cell, as in the present example, the latch circuit 13 can have the same constitution (dummy cell) as the static memory cell. In this case, the control signal DWL is supplied to the gates of the MOS transistors QN6, QN7 from the dummy word line.

[0193] The data change circuit 14 is constituted of MOS transistors QP4, QN8 connected between the nodes N1 and bN2, and MOS transistors QP5, QN9 connected between the nodes bN1 and N2. When the offset check signal OC indicates “H”, the MOS transistors QP4, QP5, QN8, QN9 are turned on, and the nodes N1 and bN2 and the nodes N2 and bN1 are electrically connected.

[0194] The disconnection circuit 15 is constituted of the P channel MOS transistor QP6 connected between the nodes N1, N2, and the P channel MOS transistor QP7 connected between the nodes bN1 ₁, bN2. When the sense amplifier enable signal SAEN indicates “H”, the nodes N1 and N2 and the nodes bN1 and bN2 are electrically disconnected.

[0195] Additionally, since the operation of the semiconductor integrated circuit of the present example is the same as that of the semiconductor integrated circuit of FIG. 7, description thereof is omitted

[0196] 3. Conclusion

[0197] According to the semiconductor integrated circuit according to the second embodiment of the present invention, the offset resulting from the process dispersion or the operation frequency of the SOI device (dispersion of the threshold voltage of the MOS transistor) is minimized by the circuit operational technique, and the drop of the operation speed and the erroneous sense operation can be prevented from being caused by the offset.

[0198] [Third Embodiment]

[0199] 1. Outline

[0200]FIG. 14 shows the semiconductor integrated circuit according to a third embodiment of the present invention.

[0201] As compared with the semiconductor integrated circuit of FIG. 3, the semiconductor integrated circuit of the present example is characterized in that the position of the latch circuit 13 is different.

[0202] For example, the case in which the present invention is applied to the semiconductor memory is considered. Then, in the example of FIG. 3, the latch circuit 13, data change circuit 14, and disconnection circuit 15 are disposed between the differential sense amplifier 11 and memory cell array. On the other hand, in the present example, the data change circuit 14 and disconnection circuit 15 are disposed between the differential sense amplifier 11 and memory cell array, and the latch circuit 13 is disposed between the differential sense amplifier 11 and data input/output circuit.

[0203] In the present example, the latch circuit 13 is disposed on the data input/output circuit side of the differential sense amplifier 11. For example, with the SRAM, the latch circuit for temporarily holding the data is usually disposed on the data input/output circuit side of the differential sense amplifier 11. Therefore, the offset information of the differential sense amplifier 11 can also be latched in the latch circuit.

[0204] The connection relation of the semiconductor integrated circuit of the present invention will be described hereinafter.

[0205] The differential sense amplifier 11 is connected between the nodes N1, bN1. The differential sense amplifier includes the constitution, for example, shown in FIG. 1. Moreover, the equalize circuit 12 for equalizing the potentials of the nodes N1, bN1 is connected between the nodes N1, bN1. Furthermore, the latch circuit 13 is connected between the nodes N1, bN1.

[0206] On the other hand, the data change circuit 14 is connected between the nodes N1 and bN2, and also connected between the nodes bN1 and N2. The data change circuit 14 has a function of electrically connecting or disconnecting the nodes N1 and bN2 and electrically connecting or disconnecting the nodes bN1 and N2.

[0207] The disconnection circuit 15 is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. The disconnection circuit 15 has a function of electrically disconnecting or connecting the nodes N1 and N2 and electrically disconnecting or connecting the nodes bN1 and bN2.

[0208] The operation principle of the semiconductor integrated circuit of FIG. 14 will briefly be described.

[0209] It is assumed that the differential sense amplifier 11 has the offset.

[0210] First, the equalize circuit 12 equalizes the potentials of the nodes N1, bN1. Thereafter, the differential sense amplifier 11 is operated. At this time, since the potential difference is not generated in two input nodes N1, bN1 of the differential sense amplifier 11, the output data is determined depending only on the offset of the differential sense amplifier 11. The output data (offset information) is latched by the latch circuit 13.

[0211] Thereafter, the data change circuit 14 electrically connects the nodes N1 and bN2 and electrically connects the nodes bN1 and N2. Moreover, the disconnection circuit 15 electrically disconnects the nodes N1 and N2 and electrically disconnects the nodes bN1 and bN2.

[0212] Therefore, the output data of the node N1 is transferred to the node bN2, and the output data of the node bN1 is transferred to the node N2.

[0213] Thereafter, the data change circuit 14 electrically disconnects the nodes N1 and bN2 and electrically disconnects the nodes bN1 and N2. Moreover, the disconnection circuit 15 electrically connects the nodes N1 and N2 and electrically connects the nodes bN1 and bN2.

[0214] Therefore, the output data of the node N2 is transferred to the node N1, and the output data of the node bN2 is transferred to the node bN1. That is, the data having the value reverse to the value of the output data of the differential sense amplifier 11, that is, the data for reducing the offset is inputted into the differential sense amplifier 11.

[0215] In this manner, according to the present invention, the data acting in the direction in which the offset of the differential sense amplifier 11 is reduced is inputted into the differential sense amplifier 11, and the offset of the differential sense amplifier 11 is minimized.

[0216] 2. Concrete Example

[0217]FIG. 15 shows a concrete example of the semiconductor integrated circuit of FIG. 14.

[0218] The differential sense amplifier 11 is constituted of P channel MOS transistors QP0, QP1 and N channel MOS transistors QN0, QN1, QN2.

[0219] The gates of the MOS transistors QP0, QN0 are connected to the node N1 and drains of the MOS transistors QP1, QN1. The gates of the MOS transistors QP1, QN1 are connected to the node bN1 and drains of the MOS transistors QP0, QN0.

[0220] The sources of the MOS transistors QP0, QP1 are connected to the inner power node Vdd, and the MOS transistor QN2 is connected between the sources of the MOS transistors QN0, QN1 and the ground point. The sense amplifier enable signal SAEN is inputted into the gate of the MOS transistor QN2.

[0221] The equalize circuit 12 is constituted of N channel MOS transistors QN3, QN4, QN5. The MOS transistor QN3 is connected between the nodes N1 and bN1, the MOS transistor QN4 is connected between the inner power node Vdd and node N1, and the MOS transistor QN5 is connected between the inner power node Vdd and node bN1.

[0222] The equalize signal EQ is inputted into the gates of the MOS transistors QN3, QN4, QN5. When the equalize signal EQ reaches “H”, both the nodes N1, bN1 are set to the inner power potential Vdd.

[0223] Additionally, in the present example, the equalize circuit 12 sets both the nodes N1, bN1 to the inner power potential Vdd. However, instead of this, for example, the equalize circuit 12 may be modified so as to set the nodes N1, bN1 to Vdd/2. In this case, the differential sense amplifier 11 is also modified, for example, as shown in FIG. 5.

[0224] The latch circuit 13 is constituted of two flip-flop connected inverters 11, 12 connected between the nodes N3, bN3, the N channel MOS transistor (transfer gate) QN6 connected between the nodes N1 and N3, and the N channel MOS transistor (transfer gate) QN7 connected between the nodes bN1 and bN3.

[0225] When the control signal DWL indicates “H”, the nodes N1 and N3 are short-circuited, and the nodes bN1 and bN3 are short-circuited.

[0226] Additionally, when the present invention is applied to the SRAM, the latch circuit 13 is already disposed in the conventional SRAM, and it is therefore unnecessary to newly dispose the circuit 13 in the conventional SRAM.

[0227] The data change circuit 14 is constituted of MOS transistors QP4, QN8 connected between the nodes N1 and bN2, and MOS transistors QP5, QN9 connected between the nodes bN1 and N2. When then offset check signal OC indicates “H”, the MOS transistors QP4, QP5, QN8, QN9 are turned on, and the nodes N1 and bN2 and the nodes N1 and bN2 are electrically connected.

[0228] The disconnection circuit 15 is constituted of the P channel MOS transistor QP6 connected between the nodes N1, N2, and the P channel MOS transistor QP7 connected between the nodes bN1, bN2. When the sense amplifier enable signal SAEN indicates “H”, the nodes N1 and N2 and the nodes bN1 and bN2 are electrically disconnected.

[0229] 3. Operation

[0230] An operation of the semiconductor integrated circuit of FIG. 15 applied to the semiconductor memory will be described.

[0231] In the normal readout mode, the data of the memory cell is read out as the potential difference of the pair of bit lines BL1, bBL1, and the potential difference is sensed and amplified by the differential sense amplifier 11.

[0232] Here, with the SOT device, unless the number of readouts of “1” data is equal to the number of readouts of “0” data with respect to the same differential sense amplifier 11 (e.g., when only the same data is continuously read out), the substrate potential of the MOS transistor having a large number of operations fluctuates, and the offset (dispersion of the threshold value of the MOS transistor) is generated in the differential sense amplifier 11.

[0233] To minimize the offset, according to the present invention, in the mode other than the normal readout mode, the following operation is continuously or intermittently performed until the offset is eliminated or sufficiently reduced.

[0234] (1) Offset Check Cycle (see FIG. 16)

[0235] The offset of the differential sense amplifier 11 is checked in this cycle.

[0236] First, it is checked whether the differential sense amplifier 11 is used in the normal operation mode, it is confirmed that the differential sense amplifier 11 is not used, and the refresh signal REFRESH is then set to “H”.

[0237] After the equalize signal EQ is set to “H”, and the nodes N1, bN1 are set to the inner power potential Vdd, the equalize signal EQ is set to “L”.

[0238] Thereafter, when the sense amplifier enable signal SAEN reaches “H”, the differential sense amplifier 11 is brought into the operative state. Since the potential difference is not generated in the input nodes N1, bN1 of the differential sense amplifier 11, the output data of the differential sense amplifier 11 is determined only by the offset of the differential sense amplifier 11.

[0239] Thereafter, when the control signal DWL reaches “H”, the MOS transistors QN6, QN7 are turned on, and therefore the data of the nodes N1, bN1 is latched by the latch circuit 13.

[0240] (2) Refresh Cycle (see FIG. 17)

[0241] The offset of the differential sense amplifier 11 is minimized in this cycle.

[0242] First, it is checked whether the differential sense amplifier 11 is used in the normal operation mode, it is confirmed that the differential sense amplifier 11 is not used, and the refresh signal REFRESH is then set to “H”.

[0243] After the equalize signal EQ is set to “H”, and the nodes N1, bN1 are set to the inner power potential Vdd, the equalize signal EQ is set to “L”.

[0244] Thereafter, when the control signal DWL is set to “H”, the data latched by the latch circuit 13 is outputted to the nodes N1, bN1.

[0245] Moreover, the offset check signal OC is set to “H”. When the offset check signal OC reaches “H”, the nodes N1 and bN2 are electrically connected, and the nodes bN1 and N2 are electrically connected. Furthermore, since the sense amplifier enable signal SAEN maintains “L”, the nodes N1 and N2 and the nodes bN1 and bN2 are electrically disconnected.

[0246] Therefore, the output data of the node N1 is transferred to the node bN2, and the output data of the node bN1 is transferred to the node N2.

[0247] Thereafter, the sense amplifier enable signal SAEN is set to “H”. When the sense amplifier enable signal SAEN reaches “H”, the differential sense amplifier 11 is brought into the operative state. Moreover, when the sense amplifier enable signal SAEN reaches “H”, the MOS transistors QP6, QP7 are turned on. Therefore, the data of the node N2 is transferred to the node N1, and the data of the node bN2 is transferred to the node bN1.

[0248] In this manner, the data reverse to the data inputted into the differential sense amplifier 11 in the normal readout mode with the high frequency is inputted into the differential sense amplifier 11 in the refresh cycle.

[0249] Therefore, in the refresh cycle, the MOS transistor different from the MOS transistor turned on by the data inputted in the normal readout mode with the high frequency is turned on, and the threshold voltage of the MOS transistor fluctuates in the direction in which the offset of the differential sense amplifier 11 is reduced.

[0250] 4. Conclusion

[0251] Even in the semiconductor integrated circuit according to the third embodiment of the present invention, the offset resulting from the process dispersion or the operation frequency of the SOI device (dispersion of the threshold voltage of the MOS transistor) is minimized by the circuit operational technique, and the drop of the operation speed and the erroneous sense operation can be prevented from being caused by the offset.

[0252] [Fourth Embodiment]

[0253] 1. Assumption

[0254]FIG. 18 shows a general constitution of the semiconductor memory.

[0255] In the semiconductor memory (e.g., SRAM), the sense amplifier is divided into a plurality of groups, and the sense amplifiers are frequently activated by a group unit.

[0256] For example, the sense amplifiers in a sense amplifier group 1 are activated (operative state) among sense amplifier groups 1 to N (N is a natural number), and the sense amplifiers in the other sense amplifier groups 2 to N are inactivated (inoperative state). In this case, for example, the data of the memory cells in a block 1 in the memory cell array 11 is outputted to the outside of the memory chip via the sense amplifier group 1, a latch group 1, a multiplexer 24, and a data input/output circuit 25.

[0257] Additionally, in this time, the sense amplifiers in the sense amplifier groups 2 to N do nothing. Therefore, with respect to the sense amplifiers in the sense amplifier groups 2 to N, in this time, a refresh operation according to the present invention (operation of checking and minimizing the offset) can be performed.

[0258] However, the sense amplifiers in the sense amplifier group are all simultaneously brought into the operative state or the inoperative state. That is, the sense amplifiers in the sense amplifier group are not selectively brought into the operative/inoperative state.

[0259] On the other hand, assuming the offset of each sense amplifier in the sense amplifier group, naturally the sense amplifiers having no offset and having the offset are mixed/disposed in the sense amplifier group. Moreover, also with respect to the sense amplifier having the offset, degrees of the offset (the dispersion of the threshold voltage of the MOS transistor) are all different.

[0260] Therefore, in this case, to minimize the offsets of all the sense amplifiers in the sense amplifier group, it is necessary to operate all the sense amplifiers until the offsets of all the sense amplifiers are minimized. As a result, very much power consumption is required in the refresh operation according to the present invention.

[0261] That is, even with respect to the sense amplifier which does not have the offset and the sense amplifier whose offset is eliminated by several refresh operations, all the refresh operations have to be performed like the sense amplifier whose offset is eliminated by a largest number of refresh operations.

[0262] To solve the problem, in the present embodiment, there is proposed a semiconductor integrated circuit in which the refresh operation can selectively be performed with respect to the respective sense amplifiers in the sense amplifier group. In this case, for the sense amplifiers whose offsets are minimized, the refresh operations are individually stopped. Only for the sense amplifiers whose offsets are not minimized, the refresh operations can individually be continued. Therefore, the present embodiment is very effective in reducing the power consumption.

[0263] 2. Outline

[0264]FIG. 19 shows the semiconductor integrated circuit according to a fourth embodiment of the present invention.

[0265] The differential sense amplifier 11 is connected between the nodes N1, bN1. Moreover, in the present example, two latch circuits 21A, 21B are connected between the nodes N1, bN1.

[0266] Additionally, in one of the latch circuits 21A, 21B, the latch circuit (denoted with the reference numeral “13” in FIGS. 3, 12, and 14) described in the first to third embodiments may be used as such. Moreover, the latch circuit disposed in the conventional semiconductor memory may also be used in one of the latch circuits 21A, 21B.

[0267] Furthermore, both the latch circuits 21A, 21B may newly be disposed separately from the latch circuit described in the first to third embodiments.

[0268] The data latched in the latch circuits 21A and 21B are inputted into a detection circuit 23. The detection circuit 23 outputs a detection signal DET based on the data of the latch circuits 21A, 21B. The detection signal DET determines whether the refresh operation (operation of minimizing the offset) according to the present invention is to be continued or stopped.

[0269] The detection signal DET is inputted into the refresh control circuit 16. The refresh control circuit 16 determines the state (“H” or “L”) of the sense amplifier enable signal SAEN based on the detection signal DET.

[0270] The operation principle of the semiconductor integrated circuit of FIG. 19 will briefly be described.

[0271] First, the data (offset information) read out of the differential sense amplifier 11 in an offset check mode during a first refresh operation is latched in the latch circuit 21A. Thereafter, the operation of minimizing the offset of the differential sense amplifier 11 is performed in the refresh cycle during the first refresh operation. When the operation of minimizing the offset ends, the data of the latch circuit 21A is transferred to the latch circuit 21B.

[0272] A second refresh operation is executed after the first refresh operation.

[0273] First, the data (offset information) is read out of the differential sense amplifier 11 in the offset check mode during the second refresh operation. The data is latched in the latch circuit 21A. Thereafter, the detection circuit 23 compares the value of the data latched by the latch circuit 21A with the value of the data latched by the latch circuit 21B.

[0274] Subsequently, it is judged based on the comparison result (detection signal DET) whether or not the refresh cycle during the second refresh operation is to be executed.

[0275] When the refresh cycle during the second refresh operation is judged to be executed, the refresh control circuit 16 sets the sense amplifier enable signal SAEN to “H”. When the refresh cycle during the second refresh operation is judged not to be executed, the sense amplifier enable signal SAEN is set to “L”.

[0276] For example, it is supposed that the data (value of the node N1) latched by the latch circuit 21A in the offset check cycle during the first refresh operation is “1”. In this case, the data (value of the node N1) read out of the differential sense amplifier 11 in the offset check cycle during the second refresh operation is “1”, it is then judged that the offset is not minimized in the first refresh operation, and the refresh cycle during the second refresh operation is executed.

[0277] Moreover, when the data (value of the node N1) read out of the differential sense amplifier 11 in the offset check cycle during the second refresh operation is “0”, the offset is judged to be minimized in the first refresh operation. The sense amplifier enable signal SAEN outputted from the refresh control circuit 16 turns to “L”, and the refresh cycle during the second refresh operation is not executed.

[0278] When the refresh cycle is not executed, the data latched by the latch circuit 21A is not transferred to the latch circuit 21B. Therefore, in this case, the data “0” read out of the differential sense amplifier 11 is not latched by the latch circuit 21B. That is, in and after the second refresh operation, the value of the data read out of the differential sense amplifier 11 in the offset check cycle (value of the data latched by the latch circuit 21A) is constantly different from the value of the data latched by the latch circuit 21B.

[0279] When a plurality of refresh operations are repeatedly performed in this manner in the present embodiment, and while the same data (the same offset information) continues to be outputted from the differential sense amplifier 11 in the offset check cycle, the refresh cycle (operation of minimizing the offset) continues to be executed. On the other hand, when and after the different data (different offset information) is outputted from the differential sense amplifier 11 in the offset check cycle, the refresh cycle (operation of minimizing the offset) is not executed.

[0280] Therefore, when and after the different data is outputted from the differential sense amplifier 11, the refresh cycle during the refresh operation is not performed, and this can contribute to the reduction of power consumption.

[0281] Additionally, even when and after the different data is outputted from the differential sense amplifier 11, the offset check mode during the refresh operation is constantly performed. The data outputted from the differential sense amplifier 11 (data latched by the latch circuit 21A) is compared with the data latched by the latch circuit 21B.

[0282] 3. Concrete Example

[0283]FIG. 20 shows a concrete example of the semiconductor integrated circuit of FIG. 19.

[0284] The detection circuit 23 is constituted of an exclusive OR circuit. An output signal of the detection circuit 23 (detection signal DET) is inputted into a NAND circuit NA1 in the refresh control circuit 16. The NAND circuit NA1 negates a logical product (executes NAND) of the refresh signal REFRESH and detection signal DET.

[0285] The output signal of the NAND circuit NA1 controls the transfer gate constituted of the MOS transistors QP8, QN12 and inverter 13. When the transfer gate opens, the sense amplifier enable signal SAEN is supplied to the differential sense amplifier 11.

[0286] 4. Operation

[0287] The operation of the semiconductor integrated circuit of FIG. 20 will be described.

[0288] First, it is confirmed that the sense amplifier in the sense amplifier group is not used in the normal operation, and thereafter the refresh signal REFRESH turns to “1”. At first, since both the data (value of the node N3) latched by the latch circuits 21A, 21B are set to “0”, the output signal of the detection circuit (exclusive OR circuit) 23 is “0”. Therefore, the output signal of the NAND circuit NA1 is “1”, and the sense amplifier enable signal SAEN is supplied to the differential sense amplifier 11.

[0289] Subsequently, the offset check mode is executed, and the data (offset information) is read out of the differential sense amplifier 11. Here, the MOS transistors QN0, QN1 in the differential sense amplifier 11 have states, for example, shown in FIG. 21, and the “1” data is outputted to the node N1.

[0290] An offset check signal OC0 reaches “H”, and the offset information (node N3=“0”, node bN3=“1”) is latched by the latch circuit 21A. Since both the data (values of the node N3) latched by the latch circuits 21A, 21B remain “0”, the output signal of the detection circuit (exclusive OR circuit) 23 remains “0”. Therefore, the output signal of the NAND circuit NA1 remains “1”, and the sense amplifier enable signal SAEN is supplied to the differential sense amplifier 11.

[0291] Thereafter, the refresh cycle is executed. That is, when a control signal DWL0 reaches “H”, the “0” data is transferred to the node N1 from the node N3 of the latch circuit 21A, and the “1” data is transferred to the node bN1 from the node bN3 of the latch circuit 21A. Thereby, the state of the differential sense amplifier 11 changes in a direction in which the offset is minimized.

[0292] At this time, a control signal DWL1 is also set to “H”. Therefore, the data of the node N3 of the latch circuit 21A is transferred to the node N3 of the latch circuit 21B, and the data of the node bN3 of the latch circuit 21A is transferred to the node bN3 of the latch circuit 21B. That is, the node N3 of the latch circuit 21B turns into “0”, and the node bN3 of the latch circuit 21B turns into “1”.

[0293] Subsequently, the offset check mode is executed again, and the data (offset information) is read out of the differential sense amplifier 11. At this time, as shown in FIG. 22, unless the offset is minimized, the data (offset information) read out into the node N1 from the differential sense amplifier 11 remains “1”.

[0294] In this case, when the offset check signal OC0 turns into “H”, the offset information (node N3=“0”, node bN3=“1”) is latched by the latch circuit 21A. Since both the data (values of the node N3) latched by the latch circuits 21A, 21B remain “0”, the output signal of the detection circuit (exclusive OR circuit) 23 remains “0”. Therefore, the output signal of the NAND circuit NA1 is “1”, and the sense amplifier enable signal SAEN is supplied to the differential sense amplifier 11.

[0295] Thereafter, the refresh cycle is executed. That is, when the control signal DWL0 turns into “H”, the “0” data is transferred to the node N1 from the node N3 of the latch circuit 21A, and the “1” data is transferred to the node bN1 from the node bN3 of the latch circuit 21A. Thereby, the state of the differential sense amplifier 11 changes in the direction in which the offset is minimized.

[0296] At this time, the control signal DWL1 is also set to “H”. Therefore, the data of the node N3 of the latch circuit 21A is transferred to the node N3 of the latch circuit 21B, and the data of the node bN3 of the latch circuit 21A is transferred to the node bN3 of the latch circuit 21B. That is, the node N3 of the latch circuit 21B turns into “0”, and the node bN3 of the latch circuit 21B turns into “1”.

[0297] Subsequently, the offset check mode is executed again, and the data (offset information) is read out of the differential sense amplifier 11. At this time, as shown in FIG. 23, if the offset is minimized, the data (offset information) read out into the node N1 from the differential sense amplifier 11 turns into “0”.

[0298] In this case, when the offset check signal OC0 turns into “H”, the offset information (node N3=“1”, node bN3=“0”) is latched by the latch circuit 21A. The data (value of the node N3) latched by the latch circuit 21A turns into “1”, and this is different from the data (value of the node N3) latched by the latch circuit 21B, that is, “0”. Therefore, the output signal of the detection circuit (exclusive OR circuit) 23 changes to “1”. Therefore, the output signal of the NAND circuit NA1 turns into “0”, and the sense amplifier enable signal SAEN is not supplied to the differential sense amplifier 11.

[0299] As a result, the sense amplifier enable signal SAEN is not supplied to the differential sense amplifier 11, and the refresh cycle is not performed.

[0300] When the refresh cycle is not executed, the control signal DWL0 does not turn into “H”, and the control signal DWL1 does not turn into “H”.

[0301] Therefore, the data of the node N3 of the latch circuit 21A is latched as such by the latch circuit 21A, and is not transferred to the latch circuit 21B. That is, the node N3 of the latch circuit 21A continues to hold “1”, and the node bN3 of the latch circuit 21A continues to hold “0”. Moreover, the node N3 of the latch circuit 21B continues to hold “0”, and the node bN3 of the latch circuit 21B continues to hold “1”.

[0302] Therefore, even in the next offset check mode, the value of the data (“1” data) read out into the node N3 of the latch circuit 21A from the differential sense amplifier 11 is different from that of the data (“0” data) latched by the node N3 of the latch circuit 21B. Thereafter, the refresh cycle is not performed.

[0303] 5. Conclusion

[0304] In the semiconductor integrated circuit according to the fourth embodiment of the present invention, in the refresh operation of the differential sense amplifier (operation of checking and minimizing the offset), when the different data is outputted from the differential sense amplifier in the offset check cycle, the refresh cycle is not subsequently performed with respect to the differential sense amplifier.

[0305] That is, the offsets of all the differential sense amplifiers are checked in the offset check cycle, and thereafter the refresh cycle is individually executed only with respect to the differential sense amplifier whose offset is not minimized. This can contribute to the reduction of power consumption.

[0306] [Fifth Embodiment]

[0307] 1. Outline

[0308] In the present embodiment, for example, there is proposed a circuit for predicting the offset of the differential sense amplifier beforehand and performing the refresh operation based on the predicted result in the first to fourth embodiments.

[0309] 2. Concrete Example

[0310]FIG. 24 shows the semiconductor integrated circuit according to a fifth embodiment of the present invention.

[0311] A latch circuit 21 is disposed for the differential sense amplifier. The latch circuit 21 latches the readout data amplified by the differential sense amplifier in the normal readout mode.

[0312] Additionally, as shown in FIG. 18, with the SRAM, one latch circuit is usually disposed for one differential sense amplifier. Therefore, when the latch circuit is used, it is unnecessary to newly dispose the latch circuit in the conventional semiconductor memory.

[0313] The readout data is constantly monitored by a counter 23A. The counter 23A increases a count value by 1, for example, when the readout data (value of a node N5) is “1”. When the readout data (value of the node N5) is “0”, the count value is decreased by 1.

[0314] That is, when the number of readouts of the “1” data is equal to the number of readouts of the “0” data in the normal readout mode, the count value of the counter 23A is 0. Moreover, when the number of readouts of the “1” data is larger than the number of readouts of the “0” data, the count value of the counter 23A is a plus value. When the number of readouts of the “0” data is larger than the number of readouts of the “1” data, the count value of the counter 23A is a minus value.

[0315] Moreover, an absolute value of the count value of the counter 23A is not less than a predetermined value (natural number of 1 or more), and then the offset of the differential sense amplifier is predicted to be large to such an extent that the value cannot be ignored. The refresh signal generation circuit 17 sets the value of the refresh signal to “H”, and executes the refresh operation.

[0316] Additionally, for the refresh operation, the refresh operation according to the first to third embodiments may also be used, or the following refresh operation may also be performed instead.

[0317] That is, when the absolute value of the count value of the counter 23A is not less than the predetermined value, the above-described offset check cycle is not performed, and the refresh cycle is executed based on the count value of the counter 23A.

[0318] For example, when the count value of the counter is the plus value, the number of readouts of the “1” data is larger than the number of readouts of the “0” data. Therefore, the refresh cycle is executed such that the readout data (value of the node N5) is “0”. Here, the counter 23A monitors the readout data (value of the node N5) even in the refresh cycle. Therefore, the refresh cycle is repeatedly performed, until the count value of the counter 23A turns into 0.

[0319] Moreover, when the count value of the counter is the minus value, the number of readouts of the “0” data is larger than the number of readouts of the “1” data. Therefore, the refresh cycle is executed such that the readout data (value of the node N5) is “1”. Here, the counter 23A monitors the readout data (value of the node N5) even in the refresh cycle. Therefore, the refresh cycle is repeatedly performed, until the count value of the counter 23A turns into 0.

[0320] 3. Conclusion

[0321] In the semiconductor integrated circuit according to the fifth embodiment of the present invention, the data inputted in the differential sense amplifier in the normal readout operation is constantly monitored by the counter, the number of inputs of the “1” data is compared with the number of inputs of the “0” data, and thereby the offset of the differential sense amplifier is predicted. Moreover, the refresh operation for minimizing the offset is performed based on the predicted result.

[0322] In this case, since the above-described offset check cycle to check the offset of the differential sense amplifier is unnecessary, time of the refresh operation can be reduced. For the semiconductor integrated circuit of the present embodiment, even with a short time in which the differential sense amplifier is not used in the normal operation, the refresh operation can sufficiently be performed. Therefore, the drop of the operation speed or the erroneous sense operation can sufficiently be prevented from being caused by the offset.

[0323] [Sixth Embodiment]

[0324]FIG. 25 shows the semiconductor integrated circuit according to a sixth embodiment of the present invention.

[0325] The differential sense amplifier 11 is connected between the nodes N1, bN1. The differential sense amplifier includes a constitution, for example, shown in FIG. 1. Moreover, the equalize circuit 12 for equalizing the potentials of the nodes N1, bN1 is connected between the nodes N1, bN1.

[0326] On the other hand, the latch circuit 13 is connected between the nodes N2, bN2. The data change circuit 14 is connected between the node N2 and an inner node of the latch circuit 13, and also connected between the node bN2 and the inner node of the latch circuit 13.

[0327] Additionally, in the present example, the nodes N1 and N2 are short-circuited, and the nodes bN1 and bN2 are short-circuited.

[0328] That is, as compared with the semiconductor integrated circuit (FIG. 3) according to the first embodiment, the semiconductor integrated circuit of the present example is characterized in that the disconnection circuit for disconnecting or connecting the nodes N1 and N2, and the nodes bN1 and bN2 is not disposed.

[0329] The operation principle of the semiconductor integrated circuit of FIG. 25 will briefly be described.

[0330] It is assumed that the differential sense amplifier 11 has the offset.

[0331] First, the equalize circuit 12 equalizes the potentials of the nodes N1, N2. Thereafter, the differential sense amplifier 11 is operated. At this time, since the potential difference is not generated in two input nodes N1, N2 of the differential sense amplifier 11, the output data is determined depending only on the offset of the differential sense amplifier 11.

[0332] The output data (offset information) is latched by the latch circuit 13 via the data change circuit 14. Here, the data change circuit 14 has a function of allowing the latch circuit 13 to latch the data having the value reverse to the value of the output data.

[0333] Thereafter, the data latched by the latch circuit 13, that is, the data having the value reverse to the value of the output data outputted from the differential sense amplifier during the offset check is inputted into the differential sense amplifier.

[0334] As described above, in the present invention, the data acting in the direction in which the offset of the differential sense amplifier 11 is reduced is inputted into the differential sense amplifier 11, and the offset of the differential sense amplifier 11 is minimized.

[0335] 2. Concrete Example

[0336]FIG. 26 shows a concrete example of the semiconductor integrated circuit of FIG. 25.

[0337] The differential sense amplifier 11 is constituted of the P channel MOS transistors QP0, QP1 and N channel MOS transistors QN0, QN1, QN2.

[0338] The gates of the MOS transistors QP0, QN0 are connected to the node N1 and the drains of the MOS transistors QP1, QN1. The gates of the MOS transistors QP1, QN1 are connected to the node bN1 and the drains of the MOS transistors QP0, QN0.

[0339] The sources of the MOS transistors QP0, QP1 are connected to the inner power node Vdd, and the MOS transistor QN2 is connected between the sources of the MOS transistors QN0, QN1 and the ground point. The sense amplifier enable signal SAEN is inputted into the gate of the MOS transistor QN2.

[0340] The equalize circuit 12 is constituted of the N channel MOS transistors QN3, QN4, QN5. The MOS transistor QN3 is connected between the nodes N1 and bN1, the MOS transistor QN4 is connected between the inner power node Vdd and node N1, and the MOS transistor QN5 is connected between the inner power node Vdd and node bN1.

[0341] The equalize signal EQ is inputted into the gates of the MOS transistors QN3, QN4, QN5. When the equalize signal EQ turns into “H”, both the nodes N1, bN1 are set to the inner power potential Vdd.

[0342] Additionally, in the present example, the equalize circuit 12 sets both the nodes N1, bN1 to the inner power potential Vdd. However, instead of this, for example, the equalize circuit 12 may be modified so as to set the nodes N1, bN1 to Vdd/2. In this case, the differential sense amplifier 11 is also modified, for example, as shown in FIG. 5.

[0343] Moreover, the present invention is not limited to the present embodiment, and the sense amplifier may have a constitution, for example, shown in FIG. 28 in all the above-described embodiments and all embodiments described later.

[0344] The latch circuit 13 is constituted of two flip-flop connected inverters I1, I2 connected between the nodes N3, bN3, the N channel MOS transistor (transfer gate) QN6 connected between nodes N2 and N3, and the N channel MOS transistor (transfer gate) QN7 connected between the nodes bN2 and bN3.

[0345] When the control signal DWL indicates “H”, the nodes N2 and N3 are short-circuited, and the nodes bN2 and bN3 are short-circuited.

[0346] Additionally, the latch circuit 13 can be constituted, for example, in the same manner as the memory cell. When the memory cell is the static memory cell, as in the present example, the latch circuit 13 can have the same constitution (dummy cell) as the static memory cell. In this case, the control signal DWL is supplied to the gates of the MOS transistors QN6, QN7 from the dummy word line.

[0347] The data change circuit 14 is constituted of the MOS transistor QN8 connected between the node N2 and the inner node bN3 of the latch circuit 13, and the MOS transistor QN9 connected between the node bN2 and the inner node N3 of the latch circuit 13.

[0348] When the offset check signal OC indicates “H”, the MOS transistors QN8, QN9 are turned on, the node N2 and the inner node bN3 of the latch circuit 13 are electrically connected, and the nodes bN2 and the inner node N3 of the latch circuit 13 are electrically connected.

[0349] The disconnection circuit 15 is disposed, for example, between the latch circuit 13 and the memory cell array, and is disposed to electrically disconnect the nodes N2, bN2 and bit line pair, and to reduce a parasitic capacity generated in the nodes N2, bN2.

[0350] 3. Operation

[0351] The operation of the semiconductor integrated circuit of FIG. 26 will be described.

[0352] In the normal readout mode, the data of the memory cell is read out as the potential difference of the pair of bit lines BL1, bBL1, and the potential difference is sensed and amplified by the differential sense amplifier 11.

[0353] Here, with the SOI device, unless the number of readouts of the “1” data is equal to the number of readouts of the “0” data with respect to the same differential sense amplifier 11 (e.g., when only the same data is continuously read out), the substrate potential of the MOS transistor having a large number of operations fluctuates, and the offset (dispersion of the threshold value of the MOS transistor) is generated in the differential sense amplifier 11.

[0354] To minimize the offset, according to the present invention, in the mode other than the normal readout mode, the following operation is continuously or intermittently performed until the offset is eliminated or sufficiently reduced.

[0355] (1) Offset Check Cycle (see FIG. 29)

[0356] The offset of the differential sense amplifier 11 is checked in this cycle.

[0357] First, it is checked whether the differential sense amplifier 11 is used in the normal operation mode. Subsequently, it is confirmed that the differential sense amplifier 11 is not used, and the refresh signal REFRESH is then set to “H”. A control signal Isolate constantly indicates “H”, and the MOS transistors QP6, QP7 are always in the off state.

[0358] After the equalize signal EQ is set to “H”, and the nodes N1, bN1 are set to the inner power potential Vdd, the equalize signal EQ is set to “L”.

[0359] Thereafter, the sense amplifier enable signal SAEN is set to “H”, and simultaneously or a little later the offset check signal OC is set to “H”.

[0360] When the sense amplifier enable signal SAEN reaches “H”, the differential sense amplifier 11 is brought into the operative state. Since the potential difference is not generated in the input nodes N1, bN1 of the differential sense amplifier 11, the output data of the differential sense amplifier 11 is determined only by the offset of the differential sense amplifier 11.

[0361] That is, one of the nodes N1, bN1 is brought into the “1” state (=Vdd), and the other node is into the “0” state (=Vss) in accordance with the offset of the differential sense amplifier 11.

[0362] Moreover, when the offset check signal OC reaches “H”, the node N2 and the inner node bN3 of the latch circuit 13 are electrically connected, and the nodes bN2 and the inner node bN3 of the latch circuit 13 are electrically connected.

[0363] Therefore, the data outputted to the node N1 is transferred to the inner node bN3 of the latch circuit 13 via the node N2, and the data outputted to the node bN1 is transferred to the inner node N3 of the latch circuit 13 via the node bN2.

[0364] For example, it is supposed that “1” is read out into the node N1 and “0” is read out into the node bN1 with the high frequency in the normal readout mode.

[0365] In this case, the threshold voltage of the MOS transistor QN0 in the differential sense amplifier 11 is lower than usual, and the threshold voltage of the MOS transistor QP1 in the differential sense amplifier 11 is higher than usual. Therefore, when the inner power potential Vdd is given to the nodes N1, bN1 in the offset check cycle, the potential of the node bN1 drops, “1” is outputted to the node N1, and “0” is outputted to the node bN1.

[0366] Moreover, the “1” data of the node N1 is transferred to the inner node bN3 of the latch circuit 13 via the data change circuit 14, and the “0” data of the node bN1 is transferred to the inner node N3 of the latch circuit 13 via the data change circuit 14. Therefore, the node N3 of the latch circuit 13 turns into the “0” state, and the node bN3 turns into the “1” state.

[0367] (2) Refresh Cycle (see FIG. 30)

[0368] The offset of the differential sense amplifier 11 is minimized in this cycle.

[0369] First, it is checked whether the differential sense amplifier 11 is used in the normal operation mode, it is confirmed that the differential sense amplifier 11 is not used, and the refresh signal REFRESH is set to “H”. The control signal Isolate always indicates “H”, and the MOS transistors QP6, QP7 are always in the off state.

[0370] After the equalize signal EQ is set to “H”, and the nodes N1, bN1 are set to the inner power potential Vdd, the equalize signal EQ is set to “L”.

[0371] Thereafter, when the control signal DWL is set to “H”, the data latched by the latch circuit 13 is transferred to the input node of the differential sense amplifier 11.

[0372] For example, when the node N3 of the latch circuit 13 is in the “0” state, and the node bN3 is in the “1” state, the “0” data is outputted to the node N1, and the “1” data is outputted to the node bN1.

[0373] Thereafter, the sense amplifier enable signal SAEN is set to “H”. When the sense amplifier enable signal SAEN reaches “H”, the differential sense amplifier 11 is brought into the operative state. Since the data of the latch circuit 13 is outputted to the input nodes N1, bN1 of the differential sense amplifier 11, the output data of the differential sense amplifier 11 is determined by the data of the latch circuit 13.

[0374] Here, the data latched by the latch circuit 13 is reverse to the data outputted from the differential sense amplifier 11 in the offset check cycle. In other words, in the refresh cycle, the data reverse to the data inputted into the differential sense amplifier 11 with the high frequency in the normal readout mode is inputted into the differential sense amplifier 11.

[0375] Therefore, in the refresh cycle, the MOS transistor different from the MOS transistor turned on by the data inputted in the normal readout mode with the high frequency is turned on, and the threshold voltage of the MOS transistor fluctuates in the direction in which the offset of the differential sense amplifier 11 is reduced.

[0376] For example, in the normal readout mode, when the “1” data is read out into the node N1 and the “0” data is read out into the node bN1 with the high frequency, the node N3 of the latch circuit 13 turns into the “0” state and the node bN3 turns into the “1” state in the offset check cycle. Therefore, in the refresh cycle, the “0” data is inputted into the input node N1 of the differential sense amplifier 11, and the “1” data is inputted into the input node bN1.

[0377] In this case, since the MOS transistors QP0, QN1 in the differential sense amplifier 11 are brought into the on state, the threshold voltage of the N channel MOS transistor QN1 drops, and the threshold voltage of the P channel MOS transistor QP1 rises. That is, the threshold voltage of the MOS transistor QN1 fluctuates in the direction in which the threshold voltage becomes equal to the threshold voltage of the MOS transistor QN0 in the state lower than usual. The threshold voltage of the MOS transistor QP0 fluctuates in the direction in which the threshold voltage becomes equal to the threshold voltage of the MOS transistor QP1 in a state higher than usual.

[0378] In this manner, since the data reverse to the data inputted into the differential sense amplifier 11 in the normal readout mode with the high frequency is inputted into the differential sense amplifier 11 in the refresh cycle, the offset of the differential sense amplifier 11 is minimized.

[0379] 4. Modification Example

[0380]FIG. 27 shows a modification example of the semiconductor integrated circuit of FIG. 26.

[0381] As compared with the semiconductor integrated circuit of FIG. 26, the semiconductor integrated circuit of the present example is characterized in that a disconnection circuit 15A is connected between the nodes N1 and N2, and between the nodes bN1 and bN2.

[0382] In this case, the MOS transistor QN8 in the data change circuit 14 is connected between the node N1 and the inner node bN3 of the latch circuit 13, and the MOS transistor QN9 in the data change circuit 14 is connected between the node bN1 and the inner node N3 of the latch circuit 13.

[0383] Additionally, since the operation is the same as the operation of the semiconductor integrated circuit of FIG. 26 (see FIGS. 29 and 30), the description thereof is omitted.

[0384] 5. Conclusion

[0385] In the semiconductor integrated circuit according to the sixth embodiment of the present invention, the offset resulting from the process dispersion or the operation frequency of the SOI device (dispersion of the threshold voltage of the MOS transistor) is minimized by the circuit operational technique, and the drop of the operation speed and the erroneous sense operation can be prevented from being caused by the offset.

[0386] [Seventh Embodiment]

[0387] 1. Outline

[0388]FIG. 31 shows the semiconductor integrated circuit according to a seventh embodiment of the present invention.

[0389] The differential sense amplifier 11 is connected between the nodes N1, bN1. The differential sense amplifier includes the constitution, for example, shown in FIG. 1. Moreover, the equalize circuit 12 for equalizing the potentials of the nodes N1, bN1 is connected between the nodes N1, bN1.

[0390] On the other hand, the latch circuit 13 is connected between the nodes N2, bN2. The data change circuit 14 is connected between the node N2 and the inner node of the latch circuit 13, and also connected between the node bN2 and the inner node of the latch circuit 13.

[0391] Additionally, in the present example, the nodes N1 and N2 are short-circuited, and the nodes bN1 and bN2 are short-circuited.

[0392] That is, as compared with the semiconductor integrated circuit (FIG. 12) according to the second embodiment, the semiconductor integrated circuit of the present example is characterized in that the disconnection circuit for disconnecting or connecting the nodes N1 and N2, and the nodes bN1 and bN2 is not disposed.

[0393] The operation principle of the semiconductor integrated circuit of FIG. 31 will briefly be described.

[0394] It is assumed that the differential sense amplifier 11 has the offset.

[0395] First, the equalize circuit 12 equalizes the potentials of the nodes N1, N2. Thereafter, the differential sense amplifier 11 is operated. At this time, since the potential difference is not generated in two input nodes N1, N2 of the differential sense amplifier 11, the output data is determined depending only on the offset of the differential sense amplifier 11.

[0396] The output data (offset information) is latched by the latch circuit 13 via the data change circuit 14. Here, the data change circuit 14 has a function of allowing the latch circuit 13 to latch the data having the value reverse to the value of the output data.

[0397] Thereafter, the data latched by the latch circuit 13, that is, the data having the value reverse to the value of the output data outputted from the differential sense amplifier during the offset check is inputted into the differential sense amplifier.

[0398] As described above, in the present invention, the data acting in the direction in which the offset of the differential sense amplifier 11 is reduced is inputted into the differential sense amplifier 11, and the offset of the differential sense amplifier 11 is minimized.

[0399] 2. Concrete Example

[0400]FIG. 32 shows a concrete example of the semiconductor integrated circuit of FIG. 31.

[0401] The differential sense amplifier 11 is constituted of the P channel MOS transistors QP0, QP1 and N channel MOS transistors QN0, QN1, QN2.

[0402] The gates of the MOS transistors QP0, QN0 are connected to the node N1 and the drains of the MOS transistors QP1, QN1. The gates of the MOS transistors QP1, QN1 are connected to the node bN1 and the drains of the MOS transistors QP0, QN0.

[0403] The sources of the MOS transistors QP0, QP1 are connected to the inner power node Vdd, and the MOS transistor QN2 is connected between the sources of the MOS transistors QN0, QN1 and the ground point. The sense amplifier enable signal SAEN is inputted into the gate of the MOS transistor QN2.

[0404] The equalize circuit 12 is constituted of the N channel MOS transistors QN3, QN4, QN5. The MOS transistor QN3 is connected between the nodes N1 and bN1, the MOS transistor QN4 is connected between the inner power node Vdd and node N1, and the MOS transistor QN5 is connected between the inner power node Vdd and node bN1.

[0405] The equalize signal EQ is inputted into the gates of the MOS transistors QN3, QN4, QN5. When the equalize signal EQ turns into “H”, both the nodes N1, bN1 are set to the inner power potential Vdd.

[0406] Additionally, in the present example, the equalize circuit 12 sets both the nodes N1, bN1 to the inner power potential Vdd. However, instead of this, for example, the equalize circuit 12 may be modified so as to set the nodes N1, bN1 to Vdd/2. In this case, the differential sense amplifier 11 is also modified, for example, as shown in FIG. 5.

[0407] Moreover, the present invention is not limited to the present embodiment, and the sense amplifier may have the constitution, for example, shown in FIG. 28 in all the above-described embodiments and all the embodiments described later.

[0408] The latch circuit 13 is constituted of two flip-flop connected inverters I1, I2 connected between the nodes N3, bN3, the N channel MOS transistor (transfer gate) QN6 connected between nodes N2 and N3, and the N channel MOS transistor (transfer gate) QN7 connected between the nodes bN2 and bN3.

[0409] When the control signal DWL indicates “H”, the nodes N2 and N3 are short-circuited, and the nodes bN2 and bN3 are short-circuited.

[0410] Additionally, the latch circuit 13 can be constituted, for example, in the same manner as the memory cell. When the memory cell is the static memory cell, as in the present example, the latch circuit 13 can have the same constitution (dummy cell) as the static memory cell. In this case, the control signal DWL is supplied to the gates of the MOS transistors QN6, QN7 from the dummy word line.

[0411] The data change circuit 14 is constituted of the MOS transistor QN8 connected between the node N2 and the inner node bN3 of the latch circuit 13, and the MOS transistor QN9 connected between the node bN2 and the inner node N3 of the latch circuit 13.

[0412] When the offset check signal OC indicates “H”, the MOS transistors QN8, QN9 are turned on, the node N2 and the inner node bN3 of the latch circuit 13 are electrically connected, and the nodes bN2 and the inner node N3 of the latch circuit 13 are electrically connected.

[0413] The disconnection circuit 15 is disposed, for example, between the latch circuit 13 and the memory cell array, and is disposed to electrically disconnect the nodes N2, bN2 and bit line pair, and to reduce the parasitic capacity generated in the nodes N2, bN2.

[0414] Additionally, since the operation of the semiconductor integrated circuit according to the present embodiment is the same as that of the semiconductor integrated circuit according to the sixth embodiment, the description thereof is omitted.

[0415] 4. Conclusion

[0416] In the semiconductor integrated circuit according to the seventh embodiment of the present invention, the offset resulting from the process dispersion or the operation frequency of the SOI device (dispersion of the threshold voltage of the MOS transistor) is minimized by the circuit operational technique, and the drop of the operation speed and the erroneous sense operation can be prevented from being caused by the offset.

[0417] [Eighth Embodiment]

[0418] 1. Outline

[0419] In the semiconductor integrated circuits according to the first, second, third, sixth, and seventh embodiments, the operation of minimizing the offset of the sense amplifier is performed for each sense amplifier. That is, the offset check is performed for each sense amplifier, and the refresh is performed to minimize the offset based on the offset check result. Moreover, the offset check and refresh are always performed for each sense amplifier during the refresh operation (when the refresh signal REFRESH indicates “H”).

[0420] Moreover, in the semiconductor integrated circuit according to the fourth embodiment, it is detected for each sense amplifier whether or not the offset is minimized. For the sense amplifier whose offset is minimized, the refresh is not subsequently performed, and the power consumption is reduced. Furthermore, in the semiconductor integrated circuit according to the fifth embodiment, the offset check is not performed, the readout data inputted into the sense amplifier is always monitored by the counter during the normal operation, the state of the sense amplifier (offset information) is predicted based on the monitor result, and the refresh is performed.

[0421] On the other hand, in the present embodiment, the offset check and refresh are performed for each sense amplifier in the same manner as in the semiconductor integrated circuits according to the first, second, third, sixth, and seventh embodiments.

[0422] Additionally, when a predetermined condition is satisfied in the present embodiment, the offset check and refresh are forcibly ended with respect to all the sense amplifiers,

[0423] For the predetermined condition, the offset of the sense amplifier whose offset resulting from a history effect (dispersion of the threshold voltage) is maximized is minimized. Here, a case in which the offset resulting from the history effect is maximized is a case in which the same data is inputted into the sense amplifier.

[0424] To solve the problem, according to the present embodiment, there are proposed: a circuit which maximizes the offset of the sense amplifier resulting from the history effect (circuit which produces a worst condition); a circuit to detect whether or not the offset of the sense amplifier is minimized; and a circuit to forcibly end the offset check and refresh with respect to all the sense amplifiers, when the offset of the sense amplifier is minimized.

[0425] 2. Concrete Example

[0426]FIG. 33 shows a first example of the semiconductor integrated circuit according to an eighth embodiment of the present invention. FIG. 34 shows a circuit constitution of an auxiliary array and corresponding sense amplifier of FIG. 33 in detail.

[0427] An auxiliary array 18A is disposed adjacent to the memory cell array 18. The auxiliary array is constituted of a plurality of cells (N channel MOS transistors) connected to one pair of bit lines BL00, bBL00.

[0428] The other end of the MOS transistor whose one end is connected to the bit line BL00 is connected to a power terminal Vdd. The other end of the MOS transistor whose one end is connected to the bit line bBL00 is connected to a ground point Vss. The gates of the respective MOS transistors are connected to word lines WL0, WL1, . . . similarly as the memory cells in the memory cell array 18. This realizes the circuit which maximizes the offset of the sense amplifier resulting from the history effect (circuit which produces the worst condition).

[0429] Additionally, the auxiliary array 18A may be disposed in the memory cell array 18.

[0430] The differential sense amplifier 11 is constituted of the P channel MOS transistors QP0, QP1 and N channel MOS transistors QN0, QN1, QN2.

[0431] The gates of the MOS transistors QP0, QN0 are connected to the node N1 and drains of the MOS transistors QP1, QN1. The gates of the MOS transistors QP1, QN1 are connected to the node bN1 and drains of the MOS transistors QP0, QN0.

[0432] The sources of the MOS transistors QP0, QP1 are connected to the inner power node Vdd, and the MOS transistor QN2 is connected between the sources of the MOS transistors QN0, QN1 and the ground point. The sense amplifier enable signal SAEN is inputted into the gate of the MOS transistor QN2.

[0433] The equalize circuit 12 is constituted of the N channel MOS transistors QN3, QN4, QN5. The MOS transistor QN3 is connected between the nodes N1 and bN1, the MOS transistor QN4 is connected between the inner power node Vdd and node N1, and the MOS transistor QN5 is connected between the inner power node Vdd and node bN1.

[0434] The equalize signal EQ is inputted into the gates of the MOS transistors QN3, QN4, QN5. When the equalize signal EQ reaches “H”, both the nodes N1 and bN1 are set to the inner power potential Vdd.

[0435] The latch circuit 13 is constituted of two flip-flop connected inverters 11, 12 connected between the nodes N3, bN3, the N channel MOS transistor (transfer gate) QN6 connected between the nodes N2 and N3, and the N channel MOS transistor (transfer gate) QN7 connected between the nodes bN2 and bN3.

[0436] When the control signal DWL indicates “H”, the nodes N2 and N3 are short-circuited, and the nodes bN2 and bN3 are short-circuited.

[0437] The data change circuit 14 is constituted of the MOS transistor QN8 connected between the node N2 and the inner node bN3 of the latch circuit 13, and the MOS transistor QN9 connected between the node bN2 and the inner node N3 of the latch circuit 13.

[0438] When the offset check signal OC indicates “H”, the MOS transistors QN8, QN9 are turned on, the node N2 and the inner node bN3 of the latch circuit 13 are electrically connected, and the nodes bN2 and the inner node N3 of the latch circuit 13 are electrically connected.

[0439] The disconnection circuit 15 is disposed, for example, between the latch circuit 13 and the auxiliary array 18A, and is disposed to electrically disconnect the nodes N2, bN2 and bit line pair BL00, bBL00, and to reduce the parasitic capacity generated in the nodes N2, bN2.

[0440] In the differential sense amplifier 11 corresponding to the auxiliary array 18A, during the normal readout operation, the data “1” is always transferred to the node N1, and the data “0” is transferred to the node bN1.

[0441] Therefore, for example, the threshold voltage of the N channel MOS transistor QN0 in the differential sense amplifier 11 is considered to be lower than the threshold voltage of the N channel MOS transistor QN1 (have the offset).

[0442] That is, in the offset check, the “1” data is outputted to the node N1, and the “0” data is outputted to the node bN1. Moreover, the “0” data is latched in the inner node N3 of the latch circuit 13, and the “1” data is latched in the inner node bN3 of the latch circuit 13.

[0443] To detect whether or not the offset is minimized with respect to the sense amplifier whose offset is maximized, the state (level) of at least one of the inner nodes N3, bN3 of the latch circuit 13 may be monitored.

[0444] In the present embodiment, the data of the inner node N3 of the latch circuit 13 is monitored. When the offset is not minimized, the data of the inner node N3 of the latch circuit 13 remains “0”. On the other hand, when the offset is minimized, the data of the inner node N3 of the latch circuit 13 changes to “1”.

[0445] A potential change of the inner node N3 of the latch circuit 13 is detected by a refresh control circuit 16A.

[0446] For example, the data of the inner node N3 of the latch circuit 13 and the refresh signal REFRESH are inputted into a NAND circuit NA2. During the refresh operation, the data of the inner node N3 is usually “0”, and the refresh signal REFRESH is “1”. Therefore, the output signal of the NAND circuit NA2 is “1”, and the sense amplifier enable signal SAEN is supplied to all the differential sense amplifiers 11.

[0447] When the offset is minimized, and the data of the inner node N3 of the latch circuit 13 changes to “1”, two input data of the NAND circuit NA2 are both “1”, and therefore the output data of the NAND circuit NA2 is “0”. Therefore, a transfer gate TG closes, and the sense amplifier enable signal SAEN is not supplied to all the differential sense amplifiers 11.

[0448] As a result, the offset check and refresh are forced to end with respect to all the sense amplifiers.

[0449]FIG. 35 shows a second example of the semiconductor integrated circuit according to the eighth embodiment of the present invention. FIGS. 36 and 37 show the circuit constitution of auxiliary arrays 1, 2 and corresponding sense amplifiers of FIG. 35 in detail.

[0450] As compared with the first example, the second example is characterized in that one row of the auxiliary array is changed to two rows of auxiliary arrays. In the first example, since there is one row of auxiliary array, any one of “0” and “1” data (the same data) is only inputted into the sense amplifier in the worst condition.

[0451] For example, in the first example, “1” is always read out into the bit line BL00, and “0” is always read out into the bit line bBL00.

[0452] However, in this case, only one of the worst conditions in the case in which the “0” data is always read out and the case in which the “1” data is always read out can be produced, and the offset cannot completely minimized with respect to all the sense amplifiers.

[0453] To solve the problem, in the second example, two circuits which produce the worst conditions are disposed adjacent to the memory cell array 18. That is, in the second example, there are disposed: an auxiliary array 18A which is disposed adjacent to the memory cell array 18 and produces a worst condition “1” so as to always read out the “1” data; and an auxiliary array 18B which produces a worst condition “2” so as to always read out the “0” data.

[0454] The semiconductor integrated circuit of the second example will concretely be described hereinafter.

[0455] The auxiliary array 18A is disposed adjacent to the memory cell array 18. The auxiliary array 18A includes a constitution shown in FIG. 36, and produces the worst condition “1” that the “1” data is always read out, that is, the worst condition that “1” is always read out into the bit line BL00.

[0456] Concretely, the other end of the MOS transistor whose one end is connected to the bit line BL00 is connected to the power terminal Vdd. The other end of the MOS transistor whose one end is connected to the bit line bBL00 is connected to the ground point Vss. The gates of the respective MOS transistors are connected to the word lines WL0, WL1, . . . similarly as the memory cells in the memory cell array 18.

[0457] This realizes the circuit which maximizes the offset of the sense amplifier resulting from the history effect (circuit which produces the worst condition “1”).

[0458] The auxiliary array 18B is disposed adjacent to the memory cell array 18. The auxiliary array 18B includes a constitution shown in FIG. 37, and produces the worst condition “0” that the “0” data is always read out, that is, the worst condition that “0” is always read out into the bit line BL00.

[0459] Concretely, the other end of the MOS transistor whose one end is connected to the bit line BL00 is connected to the ground point Vss. Moreover, the other end of the MOS transistor whose one end is connected to the bit line bBL00 is connected to the power terminal Vdd. The gates of the respective MOS transistors are connected to the word lines WL0, WL1, . . . similarly as the memory cells in the memory cell array 18.

[0460] This realizes the circuit which maximizes the offset of the sense amplifier resulting from the history effect (circuit which produces the worst condition “0”).

[0461] Additionally, the auxiliary arrays 18A, 18B may be disposed in the memory cell array 18.

[0462] The differential sense amplifier 11 is constituted of the P channel MOS transistors QP0, QP1 and N channel MOS transistors QN0, QN1, QN2.

[0463] The gates of the MOS transistors QP0, QN0 are connected to the node N1 and drains of the MOS transistors QP1, QN1. The gates of the MOS transistors QP1, QN1 are connected to the node bN1 and drains of the MOS transistors QP0, QN0.

[0464] The sources of the MOS transistors QP0, QP1 are connected to the inner power node Vdd, and the MOS transistor QN2 is connected between the sources of the MOS transistors QN0, QN1 and the ground point. The sense amplifier enable signal SAEN is inputted into the gate of the MOS transistor QN2.

[0465] The equalize circuit 12 is constituted of the N channel MOS transistors QN3, QN4, QN5. The MOS transistor QN3 is connected between the nodes N1 and bN1, the MOS transistor QN4 is connected between the inner power node Vdd and node N1, and the MOS transistor QN5 is connected between the inner power node Vdd and node bN1.

[0466] The equalize signal EQ is inputted into the gates of the MOS transistors QN3, QN4, QN5. When the equalize signal EQ reaches “H”, both the nodes N1 and bN1 are set to the inner power potential Vdd.

[0467] The latch circuit 13 is constituted of two flip-flop connected inverters 11, 12 connected between the nodes N3, bN3, the N channel MOS transistor (transfer gate) QN6 connected between the nodes N2 and N3, and the N channel MOS transistor (transfer gate) QN7 connected between the nodes bN2 and bN3.

[0468] When the control signal DWL indicates “H”, the nodes N2 and N3 are short-circuited, and the nodes bN2 and bN3 are short-circuited.

[0469] The data change circuit 14 is constituted of the MOS transistor QN8 connected between the node N2 and the inner node bN3 of the latch circuit 13, and the MOS transistor QN9 connected between the node bN2 and the inner node N3 of the latch circuit 13.

[0470] When the offset check signal OC indicates “H”, the MOS transistors QN8, QN9 are turned on, the node N2 and the inner node bN3 of the latch circuit 13 are electrically connected, and the nodes bN2 and the inner node N3 of the latch circuit 13 are electrically connected.

[0471] The disconnection circuit 15 is disposed between the latch circuit 13 and the auxiliary arrays 18A, 18B and is disposed to electrically disconnect the nodes N2, bN2 and bit line pair BL00, bBL00, and to reduce the parasitic capacity generated in the nodes N2, bN2.

[0472] In the differential sense amplifier 11 corresponding to the auxiliary array 18A, during the normal readout operation, the data “1” is always transferred to the node N1, and the data “0” is transferred to the node bN1.

[0473] Therefore, for example, the threshold voltage of the N channel MOS transistor QN0 in the differential sense amplifier 11 is considered to be lower than the threshold voltage of the N channel MOS transistor QN1 (have the offset).

[0474] That is, in the offset check, the “1” data is outputted to the node N1, and the “0” data is outputted to the node bN1. Moreover, the “0” data is latched in the inner node N3 of the latch circuit 13, and the “1” data is latched in the inner node bN3 of the latch circuit 13.

[0475] To detect whether or not the offset is minimized with respect to the sense amplifier whose offset is maximized, the state (level) of at least one of the inner nodes N3, bN3 of the latch circuit 13 may be monitored.

[0476] In the present embodiment, data A of the inner node N3 of the latch circuit 13 is monitored with respect to the auxiliary array 18A. When the offset is not minimized, the data A of the inner node N3 of the latch circuit 13 remains “0”. On the other hand, when the offset is minimized, the data A of the inner node N3 of the latch circuit 13 changes to “1”.

[0477] Similarly, in the differential sense amplifier 11 corresponding to the auxiliary array 18B, during the normal readout operation, the data “0” is always transferred to the node N1, and the data “1” is transferred to the node bN1.

[0478] Therefore, for example, the threshold voltage of the N channel MOS transistor QN1 in the differential sense amplifier 11 is considered to be lower than the threshold voltage of the N channel MOS transistor QN0 (have the offset).

[0479] That is, in the offset check, the “0” data is outputted to the node N1, and the “1” data is outputted to the node bN1. Moreover, the “1” data is latched in the inner node N3 of the latch circuit 13, and the “0” data is latched in the inner node bN3 of the latch circuit 13.

[0480] To detect whether or not the offset is minimized with respect to the sense amplifier whose offset is maximized, the state (level) of at least one of the inner nodes N3, bN3 of the latch circuit 13 may be monitored.

[0481] In the present embodiment, data B of the inner node bN3 of the latch circuit 13 is monitored with respect to the auxiliary array 18B. When the offset is not minimized, the data B of the inner node bN3 of the latch circuit 13 remains “0”. On the other hand, when the offset is minimized, the data B of the inner node bN3 of the latch circuit 13 changes to “1”.

[0482] The potential changes of the inner nodes N3, bN3 of the latch circuit 13 are detected by the refresh control circuit 16A.

[0483] For example, the data A of the inner node N3 of the latch circuit 13 of the auxiliary array 18A, data B of the inner node bN3 of the latch circuit 13 of the auxiliary array 18B, and refresh signal REFRESH are inputted into the NAND circuit NA2. During the refresh operation, the data of the inner node N3 of the auxiliary array 18A is usually “0”, the data of the inner node bN3 of the auxiliary array 18B is also usually “0”, and the refresh signal REFRESH is “1”. Therefore, the output signal of the NAND circuit NA2 is “1”, and the sense amplifier enable signal SAEN is supplied to all the differential sense amplifiers 11.

[0484] When the offset is minimized, the data A of the inner node N3 of the latch circuit 13 of the auxiliary array 18A changes to “1”, and the data B of the inner node bN3 of the latch circuit 13 of the auxiliary array 18B changes to “1”, three input data of the NAND circuit NA2 are all “1”, and therefore the output data of the NAND circuit NA2 is “0”. Therefore, the transfer gate TG closes, and the sense amplifier enable signal SAEN is not supplied to all the differential sense amplifiers 11.

[0485] As a result, the offset check and refresh are forced to end with respect to all the sense amplifiers.

[0486] 3. Conclusion

[0487] In the semiconductor integrated circuit according to the eighth embodiment, there is disposed the circuit in which the offset of the sense amplifier resulting from the history effect is maximized (circuit which produces the worst condition), concretely the auxiliary array. Additionally, the inner node of the latch circuit is monitored by the refresh control circuit. It is thereby detected whether or not the offset of the sense amplifier is minimized. Moreover, when the offset of the sense amplifier is minimized, the offset check and refresh are forced to end with respect to all the sense amplifiers.

[0488] Thereby, an end time of the refresh operation is defined, and the refresh operation is uniformly performed with respect to all the sense amplifiers.

[0489] Moreover, the end time of the refresh operation is a time in which the offset of the sense amplifier having the maximum offset is minimized. Therefore, when the refresh operation ends, the offset is naturally minimized with respect to all the sense amplifiers.

[0490] [Ninth Embodiment]

[0491] 1. Outline

[0492] In a ninth embodiment of the present invention, a case in which the present invention is applied to a programmable logic array (PLA) circuit will be described.

[0493] In the first to eighth embodiments, the case in which the present invention is applied to the semiconductor memory has been described as the concrete example. Additionally, the idea of the present invention (offset control) can be applied not only to one MOS transistor but also to various semiconductor circuits.

[0494] Then, in the ninth embodiment, a case in which the present invention is applied to a PLA circuit will be described. As a concrete example of the case in which the present invention is applied to the PLA circuit, there is considered an example in which the principles of the first to eighth embodiments are applied as such to the PLA circuit. Moreover, for example, the PLA circuit shown in the following concrete example is also considered.

[0495] 2. Concrete Example

[0496]FIG. 38 shows the semiconductor integrated circuit according to a ninth embodiment of the present invention. FIG. 39 shows a part (one column) of a logic array of FIG. 38.

[0497] The logic array is constituted of an array of a plurality of MOS transistors. Data is programmed beforehand in each MOS transistor, and predetermined output data is outputted in response to the input data.

[0498] A decoder 27 decodes the input data, and selects one of a plurality of rows of a logic array 26. The MOS transistor which exists in the selected row is turned on, and the data programmed beforehand in the MOS transistor is read out into data lines D0, bD0.

[0499] For example, when W1 reaches an “H” level, a MOS transistor 28 is turned on. At this time, the “0” data is read out into the data line D0. Moreover, when W2 reaches the “H” level, a MOS transistor 29 is turned on. At this time, the “0” data is read out into the data line bD0.

[0500] The sense amplifier 11, precharge/equalize circuit 12, and disconnection circuit 15 are the same as those described in the above-described embodiments.

[0501] In the PLA circuit, the value of the output data is uniquely determined with respect to the value of the input data. That is, the data inputted into the sense amplifier 11 can be predicted. Therefore, a refresh control circuit 16B periodically controls the output signal of the decoder 27, so that the data for minimizing the offset is inputted into the sense amplifier 11.

[0502] Additionally, with respect to the refresh control circuit 16B, as shown by a broken-line arrow, the input data is monitored, and the output signal of the decoder 27 may be controlled in accordance with the monitor result, so that the data for minimizing the offset is inputted into the sense amplifier 11.

[0503] 3. Conclusion

[0504] In the semiconductor integrated circuit according to the ninth embodiment of the present invention, the feature of the PLA circuit that the output data is uniquely determined with respect to the input data is used, and the refresh operation is periodically performed, so that the offset of the sense amplifier for use in the PLA circuit can be minimized.

[0505] [Tenth Embodiment]

[0506] 1. Outline

[0507] In a tenth embodiment of the present invention, a case in which the present invention is applied to a general logic circuit will be described. In the ninth embodiment, the case in which the present invention is applied to the PLA circuit has been described. Additionally, the present invention can also be applied to the general logic circuit.

[0508] 2. Concrete Example

[0509]FIG. 40 shows the semiconductor integrated circuit according to the tenth embodiment of the present invention.

[0510] Input data A, B, C are inputted into logic circuits 32, 33, 34 via multiplexers 30A, 30B, 30C and delay type flip-flop circuits (D-FF) 31A, 31B, 31C. The output data of the logic circuits 32, 33, 34 are inputted into delay type flip-flop circuits (D-FF) 31D, 31E.

[0511] For example, a path to the flip-flop circuit 31E from the logic circuit 34 is a critical path. Moreover, when the input data A, B, C indicate specific values, the logic circuit 34 outputs specific data. When the input data A, B, C indicate values other than the specific values, the circuit outputs the data other than the specific data.

[0512] A probability at which the input data A, B, C indicate the specific values is usually low, and the logic circuit 34 hardly outputs the specific data. In this case, the logic circuit 34 outputs the data other than the specific data with a high probability. At this time, for example, a charge accumulated in the substrate of the MOS transistor constituting the logic circuit 34 decreases.

[0513] In general, considering that the charge is accumulated in the substrate of the MOS transistor, the semiconductor integrated circuit using a SOI substrate is designed so that an operation speed is highest in the above-described case. Therefore, the logic circuit 34 outputs the data other than the specific data with the high frequency, and the charge accumulated in the substrate of the MOS transistor constituting the logic circuit 34 decreases. This means that the operation speed of the logic circuit 34 drops. Moreover, when the logic circuit 34 constitutes the critical path, the drop of the operation speed is a large problem.

[0514] To solve the problem, in the present invention, a refresh control circuit 16C is used to periodically replace the input data A, B, C with input data a, b, c having a low probability of input and indicating the specific values, and the data are inputted into the logic circuits 32, 33, 34.

[0515] That is, when the data a, b, c having the low probability of input and indicating the specific values are periodically inputted into the logic circuits 32, 33, 34, for example, the logic circuit 34 constituting the critical path outputs the specific data. Therefore, the charge accumulated in the substrate of the MOS transistor constituting the logic circuit 34 increases, and the logic circuit 34 can always be operated at an optimum operation speed.

[0516] Additionally, when the multiplexers 30A, 30B, 30C select the input data a, b, c outputted from the refresh control circuit 16C and indicating the specific values, the output signal is prevented from being outputted from the flip-flop circuits 31D, 31E by a control signal (invalid signal) in order to prevent the specific data based on the input data a, b, c having the specific values from being transferred to the subsequent circuit.

[0517] Moreover, in the present embodiment, as shown by a broken line, a detection circuit 35 is used to monitor the output data of the logic circuit 34, and a time to perform the refresh operation may also be determined based on the monitor result.

[0518] 3. Conclusion

[0519] In the semiconductor integrated circuit according to the tenth embodiment of the present invention, there is disposed the logic circuit for outputting the specific data, when the input data having the low input probability and indicating the specific value is inputted. In this case, the input data having the low input probability and indicating the specific value is inputted into the logic circuit periodically or in accordance with the monitor result (the number of outputs of the specific data and the number of outputs of the data other than the specific data).

[0520] In this case, even when the logic circuit constitutes the critical path, the logic circuit does not output only the data other than the specific data, and the logic circuit can always be operated with an optimum condition (operation speed).

[0521] [Method of Minimizing Offset]

[0522] The embodiments of the semiconductor integrated circuit according to the present invention have been described above. A method of minimizing the offset will be described hereinafter.

[0523] 1. Method 1 of minimizing the offset

[0524]FIG. 41 shows a method 1 of minimizing the offset.

[0525] This method is applied to the differential sense amplifier, and corresponds to the operation of the semiconductor integrated circuit according to the first to third embodiments.

[0526] First, the differential sense amplifier is activated in a state in which two input potentials are equalized (step ST1). At this time, the output data of the differential sense amplifier is determined depending only on the offset of the differential sense amplifier as described above.

[0527] For example, when the number of inputs of the “1” data is larger than the number of inputs of the “0” data, and the offset is generated, the “1” data is outputted. When the number of inputs of the “0” data is larger than the number of inputs of the “1” data, and the offset is generated, the “0” data is outputted.

[0528] Subsequently, the output data of the differential sense amplifier is latched by the latch circuit (step ST2).

[0529] Thereafter, the data having the value reverse to the value of the output data of the differential sense amplifier is inputted into the differential sense amplifier based on the data (latch data) latched by the latch circuit (step ST3). That is, the data reverse to the data having a high input frequency with respect to the differential sense amplifier is inputted into the differential sense amplifier. Therefore, when the steps ST1 to ST3 are repeatedly performed, a difference between the number of inputs of the “1” data and the number of inputs of the “0” data is gradually reduced, and the offset is minimized.

[0530] Additionally, a step of generating the data having the value reverse to the value of the output data of the differential sense amplifier may be performed between the steps ST1 and ST2 (A) or between the steps ST2 and ST3 (B).

[0531] When the step of generating the data having the value reverse to the value of the output data of the differential sense amplifier is added to a part A, a series of steps of FIG. 41 correspond to the operation of the semiconductor integrated circuit according to the first and second embodiments. Moreover, when the step of generating the data having the value reverse to the value of the output data of the differential sense amplifier is added to a part B, a series of steps of FIG. 41 correspond to the operation of the semiconductor integrated circuit according to the third embodiment.

[0532] 2. Method 2 of Minimizing the Offset

[0533]FIG. 42 shows a method 2 of minimizing the offset.

[0534] This method corresponds to the operation of the semiconductor integrated circuit according to the fourth embodiment.

[0535] This method is developed under an assumption of the method shown in FIG. 41. That is, the method is characterized in that the steps of FIG. 42 are added to the part A of the flowchart of FIG. 41.

[0536] That is, the differential sense amplifier is activated in the state in which two input potentials are equalized (step ST1), and the output data is outputted from the differential sense amplifier. The value of the output data is compared with the value of the latch data (step ST1).

[0537] When the value of the output data of the differential sense amplifier is the same as the value of the latch data, the offset of the differential sense amplifier is judged not to be minimized, and the step ST2 of FIG. 41 is executed. On the other hand, when the value of the output data of the differential sense amplifier is different from the value of the latch data, the offset of the differential sense amplifier can be judged to be minimized. Therefore, the steps ST2 and ST3 of FIG. 41 are omitted (step ST12).

[0538] In the above-described method 1, since the “1” data or “0” data is surely outputted in the step ST1, the data reverse to the output data is inputted into the differential sense amplifier in the step ST3 even after minimizing the offset. In this case, even when the offset is minimized, the differential sense amplifier is brought into the operative state, and the power is wasted.

[0539] On the other hand, in the method 2, after the offset is minimized (after the data different from the latch data is outputted in the step ST1, the differential sense amplifier is in the inoperative state even during the refresh operation, and therefore the power is not wasted.

[0540] 3. Method 3 of Minimizing the Offset

[0541]FIG. 43 shows a method 3 of minimizing the offset.

[0542] This method corresponds to the operation of the semiconductor integrated circuit according to the fifth embodiment.

[0543] First, the count value of the counter is increased/decreased in accordance with the value of the data inputted into the differential sense amplifier (step ST1). For example, when the “1” data is inputted, the count value of the counter is increased by 1. When the “0” data is inputted, the count value of the counter is decreased by 1.

[0544] Additionally, it is assumed that the inputted data includes both the readout data read out of the memory cell during the normal readout operation and the data inputted into the differential sense amplifier by the refresh operation according to the present invention.

[0545] Subsequently, it is judged whether or not the absolute value of the count value of the counter is more than a predetermined value (natural number of 1 or more) (step ST2).

[0546] When the count value of the counter is not less than the predetermined value, a not negligible offset is estimated to be generated in the differential sense amplifier, and the refresh operation according to the present invention is performed (step ST3).

[0547] As the refresh operation, the above-described method 1 or methods 1, 2 may be used. Instead, the data to be inputted into the differential sense amplifier may be determined only based on the count value.

[0548] In the latter case, with the count value having a plus value, the offset is estimated to be generated such that the “1” data is easily outputted to the differential sense amplifier, and the “0” data is inputted into the differential sense amplifier. Moreover, with the count value having a minus value, the offset is estimated to be generated such that the “0” data is easily outputted to the differential sense amplifier, and the “1” data is inputted into the differential sense amplifier

[0549] According to the method 3, since the offset of the differential sense amplifier can be estimated based on the count value of the counter, the time to perform the refresh operation can easily be determined. Moreover, when the offset check cycle is omitted, and the input data is determined only based on the count value, the time of the refresh operation can also be reduced.

[0550] [Others]

[0551] In the above-described embodiments, the differential sense amplifier (differential amplifier) has mainly be described. However, the principle of the present invention can also be applied to the control of the threshold voltage of the single MOS transistor or the preventing of the offset of a semiconductor circuit other than the differential sense amplifier.

[0552] Moreover, in the above-described embodiments, the application of the differential sense amplifier to the semiconductor memory has been described as the concrete example. Additionally, all semiconductor memories such as SRAM, DRAM, ROM, and flash memory can be objects.

[0553] Furthermore, the effect of the present invention supposedly appears most in the case in which the offset resulting from the fluctuation of the substrate potential in the SOI device is minimized. Naturally, the present invention is also supposedly effectively in the case in which the fluctuation of the threshold voltage by the process dispersion is minimized, or in which the potential fluctuation of a well of a device for use in a so-called well separation technique is minimized.

[0554] As described above, according to the semiconductor integrated circuit of the present invention, the offset resulting from the process dispersion or the operation frequency of the SOI device (dispersion of the threshold voltage of the MOS transistor) is minimized by a circuit operational technique, and the drop of the operation speed and the erroneous sense operation can be prevented from being caused by the offset.

[0555] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general invention concept as defined by the appended claims and their equivalents. 

What is claimed is:
 1. A semiconductor integrated circuit comprising: an inner circuit; a first circuit which supplies a first signal for obtaining output data dependent on a state of said inner circuit to said inner circuit; a latch circuit which latches said output data; and a second circuit which supplies a second signal for returning the state of said inner circuit to a normal state based on said output data to said inner circuit.
 2. A semiconductor integrated circuit according to claim 1, wherein said output data and second signal are binary data, and said second signal has a value reverse to the value of said output data.
 3. A semiconductor integrated circuit comprising: a first circuit which supplies a first signal for obtaining output data dependent on a mismatch of a threshold voltage of a MOS transistor to said MOS transistor; a latch circuit which latches said output data; and a second circuit which supplies a second signal for eliminating the mismatch of the threshold voltage of said MOS transistor based on said output data to said MOS transistor.
 4. A semiconductor integrated circuit according to claim 3, wherein said output data and second signal are binary data, and said second signal has a value reverse to the value of said output data.
 5. A semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of said first and second nodes; a latch circuit connected between third and fourth nodes; a data change circuit which controls electric connection or disconnection of said first and fourth nodes and electric connection or disconnection of said second and third nodes; and a disconnection circuit which controls electric disconnection or connection of said first and third nodes and electric disconnection or connection of said second and fourth nodes.
 6. A semiconductor integrated circuit according to claim 5, further comprising: a memory cell array including a plurality of memory cells, wherein said latch circuit is one of said plurality of memory cells.
 7. A semiconductor integrated circuit according to claim 5, wherein said data change circuit includes a MOS transistor connected between said first and fourth nodes, and a MOS transistor connected between said second and third nodes.
 8. A semiconductor integrated circuit according to claim 5, wherein said disconnection circuit includes a MOS transistor connected between said first and third nodes, and a MOS transistor connected between said second and fourth nodes.
 9. A semiconductor integrated circuit according to claim 5, wherein said disconnection circuit electrically disconnects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an operative state, and electrically connects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an inoperative state.
 10. A semiconductor integrated circuit according to claim 5, wherein said latch circuit latches data having a value reverse to a value of output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 11. A semiconductor integrated circuit according to claim 10, wherein the data having the value reverse to the value of the output data of said sense amplifier is generated by said data change circuit.
 12. A semiconductor integrated circuit according to claim 11, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said latch circuit.
 13. A semiconductor integrated circuit according to claim 5, wherein said latch circuit latches output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 14. A semiconductor integrated circuit according to claim 13, wherein said data change circuit generates data having a value reverse to a value of the output data of said sense amplifier.
 15. A semiconductor integrated circuit according to claim 14, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said data change circuit.
 16. A semiconductor integrated circuit according to claim 5, further comprising: means for bringing said sense amplifier into an operative state in a state in which the potentials of said first and second nodes are equalized and for outputting output data from said sense amplifier; means for using said data change circuit to generate data having a value reverse to a value of said output data; means for allowing said latch circuit to latch the data having the value reverse to the value of said output data; means for allowing said latch circuit to transfer the data having the value reverse to the value of said output data to said sense amplifier; and means for bringing said sense amplifier into the operative state.
 17. A semiconductor integrated circuit according to claim 5, further comprising: another latch circuit connected between said third and fourth nodes; a detection circuit which detects data of said latch circuit and data of said another latch circuit; and a refresh control circuit to stop an operation of said sense amplifier, when the data of said latch circuit is different from the data of said another latch circuit.
 18. A semiconductor integrated circuit according to claim 5, further comprising: a counter which counts the number of inputs of first data into said sense amplifier and the number of inputs of second data reverse to said first data into said sense amplifier; and a refresh signal generation circuit to output a refresh signal for executing an operation of minimizing a dispersion of a threshold voltage of a MOS transistor constituting said sense amplifier, when a difference between the number of inputs of said first data and the number of inputs of said second data indicates a constant or more value.
 19. A semiconductor integrated circuit according to claim 5, wherein said sense amplifier includes a MOS transistor formed on a SOI substrate.
 20. A semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of said first and second nodes; a latch circuit connected between said first and second nodes; a disconnection circuit which controls electric disconnection or connection of said first node and a third node and electric disconnection or connection of said second node and a fourth node; and a data change circuit which controls electric connection or disconnection of said first and fourth nodes and electric connection or disconnection of said second and third nodes.
 21. A semiconductor integrated circuit according to claim 20, further comprising: a memory cell array including a plurality of memory cells, wherein said latch circuit latches readout data read out of said plurality of memory cells.
 22. A semiconductor integrated circuit according to claim 20, wherein said data change circuit includes a MOS transistor connected between said first and fourth nodes, and a MOS transistor connected between said second and third nodes.
 23. A semiconductor integrated circuit according to claim 20, wherein said disconnection circuit includes a MOS transistor connected between said first and third nodes, and a MOS transistor connected between said second and fourth nodes.
 24. A semiconductor integrated circuit according to claim 20, wherein said disconnection circuit electrically disconnects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an operative state, and electrically connects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an inoperative state.
 25. A semiconductor integrated circuit according to claim 20, wherein said latch circuit latches data having a value reverse to a value of output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 26. A semiconductor integrated circuit according to claim 25, wherein the data having the value reverse to the value of the output data of said sense amplifier is generated by said data change circuit.
 27. A semiconductor integrated circuit according to claim 26, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said latch circuit.
 28. A semiconductor integrated circuit according to claim 20, wherein said latch circuit latches output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 29. A semiconductor integrated circuit according to claim 28, wherein said data change circuit generates data having a value reverse to a value of the output data of said sense amplifier.
 30. A semiconductor integrated circuit according to claim 29, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said data change circuit.
 31. A semiconductor integrated circuit according to claim 20, further comprising: means for bringing said sense amplifier into an operative state in a state in which the potentials of said first and second nodes are equalized and for outputting output data from said sense amplifier; means for allowing said latch circuit to latch said output data; means for using said data change circuit to generate data having a value reverse to a value of said output data; means for allowing said data change circuit to transfer the data having the value reverse to the value of said output data to said sense amplifier; and means for bringing said sense amplifier into the operative state.
 32. A semiconductor integrated circuit according to claim 20, further comprising: another latch circuit connected between said third and fourth nodes; a detection circuit which detects data of said latch circuit and data of said another latch circuit; and a refresh control circuit to stop an operation of said sense amplifier, when the data of said latch circuit is different from the data of said another latch circuit.
 33. A semiconductor integrated circuit according to claim 20, further comprising: a counter which counts the number of inputs of first data into said sense amplifier and the number of inputs of second data reverse to said first data into said sense amplifier; and a refresh signal generation circuit to output a refresh signal for executing an operation of minimizing a dispersion of a threshold voltage of a MOS transistor constituting said sense amplifier, when a difference between the number of inputs of said first data and the number of inputs of said second data indicates a constant or more value.
 34. A semiconductor integrated circuit according to claim 20, wherein said sense amplifier includes a MOS transistor formed on a SOI substrate.
 35. A semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of said first and second nodes; a latch circuit connected between said first and second nodes; and a data change circuit which controls electric connection or disconnection of said first node and a first inner node of said latch circuit and electric connection or disconnection of said second node and a second inner node of said latch circuit.
 36. A semiconductor integrated circuit according to claim 35, further comprising: a memory cell array including a plurality of memory cells, wherein said latch circuit latches readout data read out of said plurality of memory cells.
 37. A semiconductor integrated circuit according to claim 35, wherein said data change circuit includes a MOS transistor connected between said first node and first inner node, and a MOS transistor connected between said second node and second inner node.
 38. A semiconductor integrated circuit according to claim 35, wherein said latch circuit latches data having a value reverse to a value of output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 39. A semiconductor integrated circuit according to claim 38, wherein the data having the value reverse to the value of the output data of said sense amplifier is generated by said data change circuit.
 40. A semiconductor integrated circuit according to claim 39, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said latch circuit.
 41. A semiconductor integrated circuit according to claim 35, wherein said latch circuit latches output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 42. A semiconductor integrated circuit according to claim 41, wherein said data change circuit generates data having a value reverse to a value of the output data of said sense amplifier.
 43. A semiconductor integrated circuit according to claim 42, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said data change circuit.
 44. A semiconductor integrated circuit according to claim 35, further comprising: means for bringing said sense amplifier into an operative state in a state in which the potentials of said first and second nodes are equalized and for outputting output data from said sense amplifier; means for using said data change circuit to generate data having a value reverse to a value of said output data and for allowing said latch circuit to latch the data; means for allowing said latch circuit to transfer the data having the value reverse to the value of said output data to said sense amplifier; and means for bringing said sense amplifier into the operative state.
 45. A semiconductor integrated circuit according to claim 35, further comprising: another latch circuit connected between said first and second nodes; a detection circuit which detects data of said latch circuit and data of said another latch circuit; and a refresh control circuit to stop an operation of said sense amplifier, when the data of said latch circuit is different from the data of said another latch circuit.
 46. A semiconductor integrated circuit according to claim 35, further comprising: a counter which counts the number of inputs of first data into said sense amplifier and the number of inputs of second data reverse to said first data into said sense amplifier; and a refresh signal generation circuit to output a refresh signal for executing an operation of minimizing a dispersion of a threshold voltage of a MOS transistor constituting said sense amplifier, when a difference between the number of inputs of said first data and the number of inputs of said second data indicates a constant or more value.
 47. A semiconductor integrated circuit according to claim 35, wherein said sense amplifier includes a MOS transistor formed on a SOI substrate.
 48. A semiconductor integrated circuit comprising: a sense amplifier connected between first and second nodes; an equalize circuit which equalizes potentials of said first and second nodes; a latch circuit connected between third and fourth nodes; a data change circuit which controls electric connection or disconnection of said first node and a first inner node of said latch circuit and electric connection or disconnection of said second node and a second inner node of said latch circuit; and a disconnection circuit which controls electric disconnection or connection of said first and third nodes and electric disconnection or connection of said second and fourth nodes.
 49. A semiconductor integrated circuit according to claim 48, further comprising: a memory cell array including a plurality of memory cells, wherein said latch circuit latches readout data read out of said plurality of memory cells.
 50. A semiconductor integrated circuit according to claim 48, wherein said data change circuit includes a MOS transistor connected between said first node and first inner node, and a MOS transistor connected between said second node and second inner node.
 51. A semiconductor integrated circuit according to claim 48, wherein said disconnection circuit includes a MOS transistor connected between said first and third nodes, and a MOS transistor connected between said second and fourth nodes.
 52. A semiconductor integrated circuit according to claim 48, wherein said disconnection circuit electrically disconnects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an operative state, and electrically connects said first and third nodes and said second and fourth nodes, when said sense amplifier is in an inoperative state.
 53. A semiconductor integrated circuit according to claim 48, wherein said latch circuit latches data having a value reverse to a value of output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 54. A semiconductor integrated circuit according to claim 53, wherein the data having the value reverse to the value of the output data of said sense amplifier is generated by said data change circuit.
 55. A semiconductor integrated circuit according to claim 54, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said latch circuit.
 56. A semiconductor integrated circuit according to claim 48, wherein said latch circuit latches output data of said sense amplifier obtained when the potentials of said first and second nodes are equalized.
 57. A semiconductor integrated circuit according to claim 56, wherein said data change circuit generates data having a value reverse to a value of the output data of said sense amplifier.
 58. A semiconductor integrated circuit according to claim 57, wherein the data having the value reverse to the value of the output data of said sense amplifier is given to said sense amplifier from said data change circuit.
 59. A semiconductor integrated circuit according to claim 48, further comprising: means for bringing said sense amplifier into an operative state in a state in which the potentials of said first and second nodes are equalized and for outputting output data from said sense amplifier; means for using said data change circuit to generate data having a value reverse to a value of said output data and for allowing said latch circuit to latch the data; means for allowing said latch circuit to transfer the data having the value reverse to the value of said output data to said sense amplifier; and means for bringing said sense amplifier into the operative state.
 60. A semiconductor integrated circuit according to claim 48, further comprising: another latch circuit connected between said third and fourth nodes; a detection circuit which detects data of said latch circuit and data of said another latch circuit; and a refresh control circuit to stop an operation of said sense amplifier, when the data of said latch circuit is different from the data of said another latch circuit.
 61. A semiconductor integrated circuit according to claim 48, further comprising: a counter which counts the number of inputs of first data into said sense amplifier and the number of inputs of second data reverse to said first data into said sense amplifier; and a refresh signal generation circuit to output a refresh signal for executing an operation of minimizing a dispersion of a threshold voltage of a MOS transistor constituting said sense amplifier, when a difference between the number of inputs of said first data and the number of inputs of said second data indicates a constant or more value.
 62. A semiconductor integrated circuit according to claim 48, wherein said sense amplifier includes a MOS transistor formed on a SOI substrate.
 63. A semiconductor integrated circuit comprising: a memory cell array; a plurality of sense amplifier arrays corresponding to said memory cell array; an auxiliary array including a first cell connected between a first bit line and first power terminal and a second cell connected between a second bit line and second power terminal; a disconnection circuit which is connected between said first bit line and first node and between said second bit line and second node and which controls electric disconnection or connection of said first bit line and first node and electric disconnection or connection of said second bit line and second node; a sense amplifier connected between said first and second nodes; an equalize circuit which equalizes potentials of said first and second nodes; a latch circuit connected between said first and second nodes; a data change circuit which controls electric connection or disconnection of said first node and a first inner node of said latch circuit and electric connection or disconnection of said second node and a second inner node of said latch circuit; and a refresh control circuit to monitor data of said first inner node or second inner node and to stop operations of said sense amplifier and sense amplifier array, when the data changes.
 64. A semiconductor integrated circuit comprising: a memory cell array; a plurality of sense amplifier arrays corresponding to said memory cell array; a first auxiliary array including a first cell connected between a first bit line and first power terminal and a second cell connected between a second bit line and second power terminal; a first disconnection circuit which is connected between said first bit line and a first node and between said second bit line and a second node and which controls electric disconnection or connection of said first bit line and first node and electric disconnection or connection of said second bit line and second node; a first sense amplifier connected between said first and second nodes; a first equalize circuit which equalizes potentials of said first and second nodes; a first latch circuit connected between said first and second nodes; a first data change circuit which controls electric connection or disconnection of said first node and a first inner node of said latch circuit and electric connection or disconnection of said second node and a second inner node of said latch circuit; a second auxiliary array including a third cell connected between a third bit line and said second power terminal and a fourth cell connected between a fourth bit line and said first power terminal; a second disconnection circuit which is connected between said third bit line and a third node and between said fourth bit line and a fourth node and which controls electric disconnection or connection of said third bit line and third node and electric disconnection or connection of said fourth bit line and fourth node; a second sense amplifier connected between said third and fourth nodes; a second equalize circuit which equalizes potentials of said third and fourth nodes; a second latch circuit connected between said third and fourth nodes; a second data change circuit which controls electric connection or disconnection of said third node and a third inner node of said latch circuit and electric connection or disconnection of said fourth node and a fourth inner node of said latch circuit; and a refresh control circuit to monitor data of said first or second inner node and data of said third or fourth inner node and to stop operations of said first and second sense amplifiers and sense amplifier array, when these data both change.
 65. A semiconductor integrated circuit comprising: an array including a plurality of program elements; a decoder to select a first row of said array including a first program element to output first data, when input data having a specific value is inputted; a refresh control circuit which allows said decoder to select a second row of said array including a second program element to output second data different from said first data periodically or at random; and a sense amplifier which amplifies said first and second data.
 66. A semiconductor integrated circuit comprising: a logic circuit to output specific data, when first input data having a specific value is inputted; and a refresh control circuit which inputs second input data having said specific value into said logic circuit instead of said first input data periodically or at random, wherein a probability with which said first input data indicates said specific value is lower than a probability with which said first input data indicates a value other than said specific value.
 67. A semiconductor integrated circuit according to claim 66, wherein said second input data is inputted into said logic circuit with a frequency with which a probability of output of said specific data by said logic circuit is equal to a probability of output of data other than said specific data.
 68. A semiconductor integrated circuit according to claim 66, wherein said refresh control circuit outputs a signal for preventing said specific data outputted from said logic circuit from being transmitted to a subsequent circuit, when said second input data is inputted into said logic circuit.
 69. A semiconductor integrated circuit according to claim 66, further comprising: a detection circuit which monitors output data of said logic circuit, wherein said refresh control circuit determines whether or not to input said second input data into said logic circuit based on the number of outputs of said specific data by said logic circuit and the number of outputs of data other than said specific data.
 70. A method of minimizing an offset of a sense amplifier, comprising: a first step of operating said sense amplifier in a state in which two input potentials of the sense amplifier are equalized and obtaining output data of said sense amplifier; a second step of allowing a latch circuit to latch the output data of said sense amplifier; and a third step of inputting data having a value reverse to a value of the output data of said sense amplifier into said sense amplifier.
 71. A method according to claim 70, further comprising: a step of generating the data having the value reverse to the value of the output data of said sense amplifier, which is inserted between said first and second steps.
 72. A method according to claim 70, further comprising: a step of generating the data having the value reverse to the value of the output data of said sense amplifier, which is inserted between said second and third steps.
 73. A method according to claim 70, further comprising: a step of comparing the output data of said sense amplifier with data latched by said latch circuit, which is inserted between said first and second steps; and a step of executing said second and third steps, when the output data of said sense amplifier is the same as the data latched by said latch circuit and of omitting said second and third steps, when the output data of said sense amplifier is different from the data latched by said latch circuit.
 74. A method of minimizing an offset of a sense amplifier, comprising: a first step of counting the number of inputs of first data into the sense amplifier and the number of inputs of second data reverse to said first data into said sense amplifier; and a second step of executing an operation of minimizing a dispersion of a threshold voltage of a MOS transistor constituting said sense amplifier, when a difference between the number of inputs of said first data and the number of inputs of said second data indicates a constant or more value.
 75. A method according to claim 74, wherein the operation of minimizing the dispersion of the threshold voltage of said MOS transistor is performed by inputting said second data into said sense amplifier, when the number of inputs of said first data is larger than the number of inputs of said second data and by inputting said first data into said sense amplifier, when the number of inputs of said second data is larger than the number of inputs of said first data.
 76. A method according to claim 74, wherein said first step includes: counting said first or second data inputted into said sense amplifier during a normal readout operation and also counting said first or second data inputted into said sense amplifier, when the operation of minimizing the dispersion of the threshold voltage of said MOS transistor is executed. 